github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-04-23 05:17:20 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

Merge pull request #968 from jordancarlin/softfloat_updates

Browse source 
Testfloat updates
This commit is contained in:
David Harris 2024-09-29 05:18:39 -07:00 • committed by GitHub
commit ccc1ca6c47
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
13 changed files with 103 additions and 275 deletions
Download patch file Download diff file Expand all files Collapse all files

5
.gitignore vendored
View file

@ -26,9 +26,8 @@ tests/riscof/config32e.ini
tests/riscof/config64.ini
tests/riscof/riscof_work/
tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/**
tests/fp/vectors/**/*.tv
tests/fp/vectors/**/sed*
tests/fp/testfloat/*
tests/fp/vectors/*.tv
tests/fp/vectors/sed*
tests/fp/combined_IF_vectors/IF_vectors/*.tv
tests/custom/*/*/
tests/custom/*/*/*.memfile

3
bin/regression-wally
View file

@ -438,13 +438,12 @@ if (args.testfloat): # for testfloat alone, just run testfloat tests
if (args.testfloat or args.nightly): # for nightly, run testfloat along with others
testfloatsim = "questa" # change to Verilator when Issue #707 about testfloat not running Verilator is resolved
testfloatconfigs = ["fdqh_rv64gc", "fdq_rv64gc", "fdh_rv64gc", "fd_rv64gc", "fh_rv64gc", "f_rv64gc", "fdqh_rv32gc", "f_rv32gc"]
testfloatconfigs.append("fdqh_ieee_rv64gc") # run IEEE tests for single config
for config in testfloatconfigs:
tests = ["div", "sqrt", "add", "sub", "mul", "cvtint", "cvtfp", "fma", "cmp"]
if ("f_" in config):
tests.remove("cvtfp")
for test in tests:
sim_log = WALLY + "/sim/" + testfloatsim + "/logs/"+config+"_"+test+".log"
sim_log = WALLY + "/sim/" + testfloatsim + "/logs/"+config+"_"+test+".log"
tc = TestCase(
name=test,
variant=config,

5
config/derivlist.txt
View file

@ -880,11 +880,6 @@ deriv fdqh_rv64gc rv64gc
Q_SUPPORTED 1
ZFH_SUPPORTED 1
# IEEE compatible FPU
deriv fdqh_ieee_rv64gc fdqh_rv64gc
IEEE754 1
#### MORE DIVIDER variants
#### F_only, RK variable

13
examples/fp/fpcalc/Makefile
View file

@ -1,15 +1,10 @@
# Makefile
# fpcalc Makefile
CC = gcc
CFLAGS = -O3 -Wno-format-overflow
# Link against the riscv-isa-sim version of SoftFloat rather than
# the regular version to get RISC-V NaN behavior
IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat
LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a -lm -lquadmath
#IFLAGS = -I../../../addins/berkeley-softfloat-3/source/include/
#LIBS = ../../../addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
IFLAGS = -I$(WALLY)/addins/berkeley-softfloat-3/source/include/
LIBS = $(WALLY)/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
SRCS = $(wildcard *.c)
PROGS = $(patsubst %.c,%,$(SRCS))
all: $(PROGS)
@ -17,5 +12,5 @@ all: $(PROGS)
%: %.c
$(CC) $(CFLAGS) -DSOFTFLOAT_FAST_INT64 $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
clean:
clean:
rm -f $(PROGS)

15
examples/fp/softfloat_demo/Makefile
View file

@ -1,22 +1,17 @@
# Makefile
# softfloat_demo Makefile
CC = gcc
CFLAGS = -O3
LFLAGS = -L.
# Link against the riscv-isa-sim version of SoftFloat rather than
# the regular version to get RISC-V NaN behavior
#IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat
#LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a -lm -lquadmath
IFLAGS = -I../../../addins/berkeley-softfloat-3/source/include/
LIBS = ../../../addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
IFLAGS = -I$(WALLY)/addins/berkeley-softfloat-3/source/include/
LIBS = $(WALLY)/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
SRCS = $(wildcard *.c)
PROGS = $(patsubst %.c,%,$(SRCS))
PROGS = $(patsubst %.c,%,$(SRCS))
all: $(PROGS)
%: %.c
$(CC) $(CFLAGS) -DSOFTFLOAT_FAST_INT64 $(IFLAGS) $(LFLAGS) -o $@ $< $(LIBS)
clean:
clean:
rm -f $(PROGS)

9
examples/fp/sqrttest/Makefile
View file

@ -4,14 +4,9 @@ CC = gcc
CFLAGS = -O3
LIBS = -lm
LFLAGS = -L.
# Link against the riscv-isa-sim version of SoftFloat rather than
# the regular version to get RISC-V NaN behavior
IFLAGS = -I$(RISCV)/riscv-isa-sim/softfloat
LIBS = $(RISCV)/riscv-isa-sim/build/libsoftfloat.a
#IFLAGS = -I../../../addins/berkeley-softfloat-3/source/include/
#LIBS = ../../../addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a
IFLAGS = -I$(WALLY)/addins/berkeley-softfloat-3/source/include/
LIBS = $(WALLY)/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/softfloat.a -lm -lquadmath
SRCS = $(wildcard *.c)
PROGS = $(patsubst %.c,%,$(SRCS))
all: $(PROGS)

20
testbench/testbench_fp.sv
View file

@ -33,22 +33,7 @@ module testbench_fp;
parameter string TEST="none"; // choices are cvtint, cvtfp, cmp, add, sub, mul, div, sqrt, fma; all does not check properly
parameter string TEST_SIZE="all";
`include "parameter-defs.vh"
`ifdef VERILATOR
import "DPI-C" function string getenvval(input string env_name);
string WALLY_DIR = getenvval("WALLY");
`elsif VCS
import "DPI-C" function string getenv(input string env_name);
string WALLY_DIR = getenv("WALLY");
`else
string WALLY_DIR = "$WALLY";
`endif
string FP_TESTS = {WALLY_DIR, "/tests/fp/vectors"};
string pp;
if (P.IEEE754) assign pp = {FP_TESTS, "/ieee/"};
else assign pp = {FP_TESTS, "/riscv/"};
`include "parameter-defs.vh"
parameter MAXVECTORS = 8388610;
@ -671,6 +656,7 @@ module testbench_fp;
// Read the first test
initial begin
static string pp = `PATH;
string testname;
string tt0;
tt0 = $sformatf("%s", Tests[TestNum]);
@ -1009,7 +995,7 @@ module testbench_fp;
// clear the vectors
for(int i=0; i<MAXVECTORS; i++) TestVectors[i] = '1;
// read next files
$readmemh({pp, Tests[TestNum]}, TestVectors);
$readmemh({`PATH, Tests[TestNum]}, TestVectors);
// set the vector index back to 0
VectorNum = 0;
// incemet the operation if all the rounding modes have been tested

1
testbench/tests_fp.vh
View file

@ -24,6 +24,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
`define PATH "../../tests/fp/vectors/"
`define ADD_OPCTRL 3'b110
`define MUL_OPCTRL 3'b100
`define SUB_OPCTRL 3'b111

27
tests/fp/Makefile
View file

@ -2,28 +2,35 @@
# Floating Point Tests Makefile for CORE-V-Wally
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
TESTFLOATS := testfloat/ieee/testfloat_gen testfloat/riscv/testfloat_gen
SOFTFLOAT_DIR := ${WALLY}/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC
TESTFLOAT_DIR := ${WALLY}/addins/berkeley-testfloat-3/build/Linux-x86_64-GCC
.PHONY: all vectors combined_IF_vectors testfloat clean
.PHONY: all softfloat testfloat vectors combined_IF_vectors clean
all: vectors combined_IF_vectors
vectors: ${TESTFLOATS}
softfloat: ${SOFTFLOAT_DIR}/softfloat.a
testfloat: ${TESTFLOAT_DIR}/testfloat_gen
vectors: testfloat
$(MAKE) -C ${WALLY}/tests/fp/vectors
combined_IF_vectors: ${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src vectors
cd ${WALLY}/tests/fp/combined_IF_vectors \
&& ./create_IF_vectors.sh
${TESTFLOATS}: testfloat
testfloat:
$(MAKE) -C testfloat
clean:
$(MAKE) -C vectors clean
$(MAKE) -C testfloat clean
$(MAKE) -C ${WALLY}/tests/fp/vectors clean
$(MAKE) -C ${SOFTFLOAT_DIR} clean
$(MAKE) -C ${TESTFLOAT_DIR} clean
rm -f ${WALLY}/tests/fp/combined_IF_vectors/IF_vectors/*.tv
${SOFTFLOAT_DIR}/softfloat.a:
$(MAKE) SPECIALIZE_TYPE=RISCV -C ${SOFTFLOAT_DIR}
${TESTFLOAT_DIR}/testfloat_gen: ${SOFTFLOAT_DIR}/softfloat.a
$(MAKE) -C ${TESTFLOAT_DIR}
${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src:
@$(error "riscv-arch-tests must be generated first. Run make from $$WALLY")

47
tests/fp/testfloat/Makefile
View file

@ -1,47 +0,0 @@
# Jordan Carlin, jcarlin@hmc.edu, August 2024
# Makefile to generate RISCV and IEEE varaints of Testfloat for CORE-V-Wally
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
# Makefile to build testfloat and softfloat executables for IEEE and RISC-V floating point variants
# Disable parallel execution because both versions of softfloat/testfloat use the same build directory
.NOTPARALLEL:
.SECONDEXPANSION:
TESTFLOATS := ieee riscv
SOFTFLOAT_BUILD_DIR := ${WALLY}/addins/berkeley-softfloat-3/build/Linux-x86_64-GCC/
TESTFLOAT_BUILD_DIR := ${WALLY}/addins/berkeley-testfloat-3/build/Linux-x86_64-GCC/
TESTFLOAT_EXECUTABLES := testfloat testfloat_gen testfloat_ver testsoftfloat timesoftfloat
ORIGINAL_TESTFLOAT_EXECUTABLES := $(foreach item,${TESTFLOAT_EXECUTABLES},$(patsubst %,${TESTFLOAT_BUILD_DIR}%,${item}))
.PHONY: all ieee-softfloat riscv-softfloat ${TESTFLOATS} testfloat clean
all: riscv ieee
${TESTFLOATS}: dir_$$@ $$@/testfloat_gen
.PRECIOUS: %/testfloat_gen
%/testfloat_gen:
$(MAKE) $*-softfloat
$(MAKE) testfloat
cp -r ${ORIGINAL_TESTFLOAT_EXECUTABLES} $*/
ieee-softfloat:
$(MAKE) -C $(SOFTFLOAT_BUILD_DIR) clean
$(MAKE) -C $(SOFTFLOAT_BUILD_DIR)
riscv-softfloat:
$(MAKE) -C $(SOFTFLOAT_BUILD_DIR) clean
$(MAKE) SPECIALIZE_TYPE=RISCV -C $(SOFTFLOAT_BUILD_DIR)
testfloat:
$(MAKE) -C $(TESTFLOAT_BUILD_DIR) clean
$(MAKE) -C $(TESTFLOAT_BUILD_DIR)
dir_%:
mkdir -p $*
clean:
$(MAKE) -C $(SOFTFLOAT_BUILD_DIR) clean
$(MAKE) -C $(TESTFLOAT_BUILD_DIR) clean
rm -f ieee/* riscv/*

77
tests/fp/vectors/Makefile Normal file → Executable file
View file

@ -1,16 +1,75 @@
# Jordan Carlin, jcarlin@hmc.edu, September 20 2024
# Makefile to generate floating point testvectors for CORE-V-Wally
# Makefile to generate RISCV floating point testvectors for CORE-V-Wally
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
.PHONY: ieee riscv clean
all: ieee riscv
.DELETE_ON_ERROR:
.ONESHELL:
SHELL := /bin/bash
ieee:
$(MAKE) -C ieee
TESTFLOAT_DIR := ${WALLY}/addins/berkeley-testfloat-3/build/Linux-x86_64-GCC
TESTFLOAT_GEN := ${TESTFLOAT_DIR}/testfloat_gen
riscv:
$(MAKE) -C riscv
# List of testvectors to generate. Each rounding mode will be generated for each test.
cvtint := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \
ui64_to_f16 ui64_to_f32 ui64_to_f64 ui64_to_f128 \
i32_to_f16 i32_to_f32 i32_to_f64 i32_to_f128 \
i64_to_f16 i64_to_f32 i64_to_f64 i64_to_f128 \
f16_to_ui32 f32_to_ui32 f64_to_ui32 f128_to_ui32 \
f16_to_ui64 f32_to_ui64 f64_to_ui64 f128_to_ui64
cvtfp := f16_to_i32 f32_to_i32 f64_to_i32 f128_to_i32 \
f16_to_i64 f32_to_i64 f64_to_i64 f128_to_i64 \
f16_to_f32 f16_to_f64 f16_to_f128 \
f32_to_f16 f32_to_f64 f32_to_f128 \
f64_to_f16 f64_to_f32 f64_to_f128 \
f128_to_f16 f128_to_f32 f128_to_f64
add := f16_add f32_add f64_add f128_add
sub := f16_sub f32_sub f64_sub f128_sub
mul := f16_mul f32_mul f64_mul f128_mul
div := f16_div f32_div f64_div f128_div
sqrt := f16_sqrt f32_sqrt f64_sqrt f128_sqrt
eq := f16_eq f32_eq f64_eq f128_eq
le := f16_le f32_le f64_le f128_le
lt := f16_lt f32_lt f64_lt f128_lt
mulAdd := f16_mulAdd f32_mulAdd f64_mulAdd f128_mulAdd
tests := $(cvtfp) $(cvtint) $(add) $(sub) $(mul) $(div) $(sqrt) $(eq) $(le) $(lt) $(mulAdd)
# Set rounding modes and extensions
rne: ROUND_MODE := rnear_even
rne: ROUND_EXT := rne
rz: ROUND_MODE := rminMag
rz: ROUND_EXT := rz
ru: ROUND_MODE := rmax
ru: ROUND_EXT := ru
rd: ROUND_MODE := rmin
rd: ROUND_EXT := rd
rnm: ROUND_MODE := rnear_maxMag
rnm: ROUND_EXT := rnm
.PHONY: all rne rz ru rd rnm clean
# Generate all test vectors
all: rne rz ru rd rnm
# Generate test vectors for each rounding mode
rne: $(addsuffix _rne.tv, $(tests))
rz: $(addsuffix _rz.tv, $(tests))
ru: $(addsuffix _ru.tv, $(tests))
rd: $(addsuffix _rd.tv, $(tests))
rnm: $(addsuffix _rnm.tv, $(tests))
# Rule to generate individual test vectors
%.tv: ${TESTFLOAT_GEN}
@echo Creating $@ vectors
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi
@if [[ "$*" =~ "to_i" ]] || [[ "$*" =~ "to_u" ]] ; then exact="-exact" ; else exact="" ; fi
${TESTFLOAT_GEN} -tininessafter -level $$level $$exact -$(ROUND_MODE) $(patsubst %_$(ROUND_EXT).tv, %, $@) > $@
@sed -i 's/ /_/g' $@
# Generate TestFloat first if necessary
${TESTFLOAT_GEN}:
$(MAKE) -C ${WALLY}/tests/fp testfloat
clean:
$(MAKE) -C ieee clean
$(MAKE) -C riscv clean
rm -f *.tv
rm -f sed*

78
tests/fp/vectors/ieee/Makefile
View file

@ -1,78 +0,0 @@
# Jordan Carlin, jcarlin@hmc.edu, September 20 2024
# Makefile to generate IEEE floating point testvectors for CORE-V-Wally
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
.DELETE_ON_ERROR:
.SECONDEXPANSION:
.ONESHELL:
# MAKEFLAGS += --no-print-directory
SHELL := /bin/bash
VECTOR_TYPE := ieee
TESTFLOAT_DIR := ${WALLY}/tests/fp/testfloat
TESTFLOAT_GEN := ${TESTFLOAT_DIR}/${VECTOR_TYPE}/testfloat_gen
# List of testvectors to generate. Each rounding mode will be generated for each test.
cvtint := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \
ui64_to_f16 ui64_to_f32 ui64_to_f64 ui64_to_f128 \
i32_to_f16 i32_to_f32 i32_to_f64 i32_to_f128 \
i64_to_f16 i64_to_f32 i64_to_f64 i64_to_f128 \
f16_to_ui32 f32_to_ui32 f64_to_ui32 f128_to_ui32 \
f16_to_ui64 f32_to_ui64 f64_to_ui64 f128_to_ui64
cvtfp := f16_to_i32 f32_to_i32 f64_to_i32 f128_to_i32 \
f16_to_i64 f32_to_i64 f64_to_i64 f128_to_i64 \
f16_to_f32 f16_to_f64 f16_to_f128 \
f32_to_f16 f32_to_f64 f32_to_f128 \
f64_to_f16 f64_to_f32 f64_to_f128 \
f128_to_f16 f128_to_f32 f128_to_f64
add := f16_add f32_add f64_add f128_add
sub := f16_sub f32_sub f64_sub f128_sub
mul := f16_mul f32_mul f64_mul f128_mul
div := f16_div f32_div f64_div f128_div
sqrt := f16_sqrt f32_sqrt f64_sqrt f128_sqrt
eq := f16_eq f32_eq f64_eq f128_eq
le := f16_le f32_le f64_le f128_le
lt := f16_lt f32_lt f64_lt f128_lt
mulAdd := f16_mulAdd f32_mulAdd f64_mulAdd f128_mulAdd
tests := $(cvtfp) $(cvtint) $(add) $(sub) $(mul) $(div) $(sqrt) $(eq) $(le) $(lt) $(mulAdd)
# Set rounding modes and extensions
rne: ROUND_MODE := rnear_even
rne: ROUND_EXT := rne
rz: ROUND_MODE := rminMag
rz: ROUND_EXT := rz
ru: ROUND_MODE := rmax
ru: ROUND_EXT := ru
rd: ROUND_MODE := rmin
rd: ROUND_EXT := rd
rnm: ROUND_MODE := rnear_maxMag
rnm: ROUND_EXT := rnm
.PHONY: all rne rz ru rd rnm clean
all: rne rz ru rd rnm
# Generate test vectors for each rounding mode
rne: $(addsuffix _rne.tv, $(tests))
rz: $(addsuffix _rz.tv, $(tests))
ru: $(addsuffix _ru.tv, $(tests))
rd: $(addsuffix _rd.tv, $(tests))
rnm: $(addsuffix _rnm.tv, $(tests))
# Rule to generate individual test vectors
%.tv: ${TESTFLOAT_GEN}
@echo "Creating $(VECTOR_TYPE) $@ vectors"
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi
@if [[ "$*" =~ "to_i" ]] || [[ "$*" =~ "to_u" ]] ; then exact="-exact" ; else exact="" ; fi
${TESTFLOAT_GEN} -tininessafter -level $$level $$exact -$(ROUND_MODE) $(patsubst %_$(ROUND_EXT).tv, %, $@) > $@
@sed -i 's/ /_/g' $@
# Appropriate testfloat_gen must exist
${TESTFLOAT_GEN}:
$(MAKE) -C ${TESTFLOAT_DIR} ${VECTOR_TYPE}
clean:
rm -f *.tv
rm -f sed*

78
tests/fp/vectors/riscv/Makefile
View file

@ -1,78 +0,0 @@
# Jordan Carlin, jcarlin@hmc.edu, September 20 2024
# Makefile to generate RISCV floating point testvectors for CORE-V-Wally
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
.DELETE_ON_ERROR:
.SECONDEXPANSION:
.ONESHELL:
# MAKEFLAGS += --no-print-directory
SHELL := /bin/bash
VECTOR_TYPE := riscv
TESTFLOAT_DIR := ${WALLY}/tests/fp/testfloat
TESTFLOAT_GEN := ${TESTFLOAT_DIR}/${VECTOR_TYPE}/testfloat_gen
# List of testvectors to generate. Each rounding mode will be generated for each test.
cvtint := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \
ui64_to_f16 ui64_to_f32 ui64_to_f64 ui64_to_f128 \
i32_to_f16 i32_to_f32 i32_to_f64 i32_to_f128 \
i64_to_f16 i64_to_f32 i64_to_f64 i64_to_f128 \
f16_to_ui32 f32_to_ui32 f64_to_ui32 f128_to_ui32 \
f16_to_ui64 f32_to_ui64 f64_to_ui64 f128_to_ui64
cvtfp := f16_to_i32 f32_to_i32 f64_to_i32 f128_to_i32 \
f16_to_i64 f32_to_i64 f64_to_i64 f128_to_i64 \
f16_to_f32 f16_to_f64 f16_to_f128 \
f32_to_f16 f32_to_f64 f32_to_f128 \
f64_to_f16 f64_to_f32 f64_to_f128 \
f128_to_f16 f128_to_f32 f128_to_f64
add := f16_add f32_add f64_add f128_add
sub := f16_sub f32_sub f64_sub f128_sub
mul := f16_mul f32_mul f64_mul f128_mul
div := f16_div f32_div f64_div f128_div
sqrt := f16_sqrt f32_sqrt f64_sqrt f128_sqrt
eq := f16_eq f32_eq f64_eq f128_eq
le := f16_le f32_le f64_le f128_le
lt := f16_lt f32_lt f64_lt f128_lt
mulAdd := f16_mulAdd f32_mulAdd f64_mulAdd f128_mulAdd
tests := $(cvtfp) $(cvtint) $(add) $(sub) $(mul) $(div) $(sqrt) $(eq) $(le) $(lt) $(mulAdd)
# Set rounding modes and extensions
rne: ROUND_MODE := rnear_even
rne: ROUND_EXT := rne
rz: ROUND_MODE := rminMag
rz: ROUND_EXT := rz
ru: ROUND_MODE := rmax
ru: ROUND_EXT := ru
rd: ROUND_MODE := rmin
rd: ROUND_EXT := rd
rnm: ROUND_MODE := rnear_maxMag
rnm: ROUND_EXT := rnm
.PHONY: all rne rz ru rd rnm clean
all: rne rz ru rd rnm
# Generate test vectors for each rounding mode
rne: $(addsuffix _rne.tv, $(tests))
rz: $(addsuffix _rz.tv, $(tests))
ru: $(addsuffix _ru.tv, $(tests))
rd: $(addsuffix _rd.tv, $(tests))
rnm: $(addsuffix _rnm.tv, $(tests))
# Rule to generate individual test vectors
%.tv: ${TESTFLOAT_GEN}
@echo "Creating $(VECTOR_TYPE) $@ vectors"
@if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi
@if [[ "$*" =~ "to_i" ]] || [[ "$*" =~ "to_u" ]] ; then exact="-exact" ; else exact="" ; fi
${TESTFLOAT_GEN} -tininessafter -level $$level $$exact -$(ROUND_MODE) $(patsubst %_$(ROUND_EXT).tv, %, $@) > $@
@sed -i 's/ /_/g' $@
# Appropriate testfloat_gen must exist
${TESTFLOAT_GEN}:
$(MAKE) -C ${TESTFLOAT_DIR} ${VECTOR_TYPE}
clean:
rm -f *.tv
rm -f sed*