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Resolved pmpaddrdec merge

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This commit is contained in:
David Harris 2025-05-08 15:07:52 -07:00
commit e3ae285a8e
203 changed files with 6075 additions and 521 deletions
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6
testbench/common/functionName.sv
View file

@ -93,9 +93,9 @@ module functionName import cvw::*; #(parameter cvw_t P) (
end
end // while (left <= right)
// if the element pc is now found, right and left will be equal at this point.
// we need to check if pc is less than the array at left or greather.
// we need to check if pc is less than the array at left or greater.
// if it is less than pc, then we select left as the index.
// if it is greather we want 1 less than left.
// if it is greater we want 1 less than left.
if (array[left] < pc) begin
minval = array[left];
mid = left;
@ -120,7 +120,7 @@ module functionName import cvw::*; #(parameter cvw_t P) (
// initial begin
always @ (negedge reset) begin
// cannot readmemh directoy to a dynmaic array. Sad times :(
// cannot readmemh directly to a dynamic array. Sad times :(
// Let's initialize a static array with FFFF_FFFF for all addresses.
// Then we can readmemh and finally copy to the dynamic array.

6
testbench/common/loggers.sv
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@ -126,8 +126,8 @@ module loggers import cvw::*; #(parameter cvw_t P,
assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
end else begin
// default start condiction is reset
// default end condiction is end of test (DCacheFlushDone)
// default start condition is reset
// default end condition is end of test (DCacheFlushDone)
//assign StartSampleFirst = reset;
//flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
//assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
@ -221,7 +221,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b1000 ? "Z" : // cbo.zero
dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0001 ? "V" : // cbo.inval should just clear the valid and dirty bits
dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0010 ? "C" : // cbo.clean should act like a read in terms of the lru, but clears the dirty bit
dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0100 ? "L" : // cbo.flush should just clear and the valid and drity bits
dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0100 ? "L" : // cbo.flush should just clear and the valid and dirty bits
"NULL";
end

4
testbench/common/ramxdetector.sv
View file

@ -4,7 +4,7 @@
// Written: David_Harris@hmc.edu
// Modified: 2 July 2023
//
// Purpose: Detects if the processor is attempting to read unitialized RAM
// Purpose: Detects if the processor is attempting to read uninitialized RAM
//
// A component of the Wally configurable RISC-V project.
//
@ -39,7 +39,7 @@ module ramxdetector #(parameter XLEN, LLEN) (
/* verilator lint_off WIDTHXZEXPAND */
if (MemReadM & ~LSULoadAccessFaultM & (ReadDataM === 'bx)) begin
/* verilator lint_on WIDTHXZEXPAND */
$display("WARNING: Attempting to read from unitialized RAM. Processor may go haywire if it uses x value. But this is normal in WALLY-mmu and ExceptionInstr tests.");
$display("WARNING: Attempting to read from uninitialized RAM. Processor may go haywire if it uses x value. But this is normal in WALLY-mmu and ExceptionInstr tests.");
$display(" PCM = %x InstrM = %x (%s), IEUAdrM = %x", PCM, InstrM, InstrMName, IEUAdrM);
//$stop;
end

4
testbench/common/riscvassertions.sv
View file

@ -33,10 +33,10 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
assert (P.F_SUPPORTED | !P.ZFH_SUPPORTED) else $fatal(1, "Can't support half-precision fp (ZFH) without supporting float (F)");
assert (P.DCACHE_SUPPORTED | !P.F_SUPPORTED | P.FLEN <= P.XLEN) else $fatal(1, "Data cache required to support FLEN > XLEN because AHB/DTIM bus width is XLEN");
assert (P.I_SUPPORTED ^ P.E_SUPPORTED) else $fatal(1, "Exactly one of I and E must be supported");
assert (P.DCACHE_WAYSIZEINBYTES <= 4096 | (!P.DCACHE_SUPPORTED) | P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (P.DCACHE_WAYSIZEINBYTES <= 4096 | (!P.DCACHE_SUPPORTED) | P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and virtual memory is enabled (to prevent aliasing)");
assert (P.DCACHE_LINELENINBITS >= 128 | (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
assert (P.DCACHE_LINELENINBITS < P.DCACHE_WAYSIZEINBYTES*8) else $fatal(1, "DCACHE_LINELENINBITS must be smaller than way size");
assert (P.ICACHE_WAYSIZEINBYTES <= 4096 | (!P.ICACHE_SUPPORTED) | P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (P.ICACHE_WAYSIZEINBYTES <= 4096 | (!P.ICACHE_SUPPORTED) | P.VIRTMEM_SUPPORTED == 0) else $fatal(1, "ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and virtual memory is enabled (to prevent aliasing)");
assert (P.ICACHE_LINELENINBITS >= 32 | (!P.ICACHE_SUPPORTED)) else $fatal(1, "ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
assert (P.ICACHE_LINELENINBITS < P.ICACHE_WAYSIZEINBYTES*8) else $fatal(1, "ICACHE_LINELENINBITS must be smaller than way size");
assert (2**$clog2(P.DCACHE_LINELENINBITS) == P.DCACHE_LINELENINBITS | (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must be a power of 2");

2
testbench/common/rvvitbwrapper.sv
View file

@ -45,7 +45,7 @@ module rvvitbwrapper import cvw::*; #(parameter cvw_t P,
localparam TOTAL_CSRS = 36;
// pipeline controlls
// pipeline controls
logic StallE, StallM, StallW, FlushE, FlushM, FlushW;
// required
logic [P.XLEN-1:0] PCM;

2
testbench/sdc/sd_defines.h
View file

@ -49,7 +49,7 @@
`endif
//SD-Clock Defines ---------
//Use bus clock or a seperate clock
//Use bus clock or a separate clock
`define SDC_CLK_BUS_CLK
//`define SDC_CLK_SEP

18
testbench/testbench.sv
View file

@ -264,7 +264,7 @@ module testbench;
// Do this in parts so it easier to verify
// part 1: build a version which echos the same behavior as the below code, but does not drive anything
// part 2: drive some of the controls
// part 3: drive all logic and remove old inital and always @ negedge clk block
// part 3: drive all logic and remove old initial and always @ negedge clk block
typedef enum logic [3:0]{STATE_TESTBENCH_RESET,
STATE_INIT_TEST,
@ -407,7 +407,7 @@ module testbench;
end
// declare memory labels that interest us, the updateProgramAddrLabelArray task will find
// the addr of each label and fill the array. To expand, add more elements to this array
// and initialize them to zero (also initilaize them to zero at the start of the next test)
// and initialize them to zero (also initialize them to zero at the start of the next test)
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, memfilename, WALLY_DIR, ProgramAddrLabelArray);
end
if(Validate) begin
@ -682,7 +682,7 @@ module testbench;
InstrM, InstrW,
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
// watch for problems such as lockup, reading unitialized memory, bad configs
// watch for problems such as lockup, reading uninitialized memory, bad configs
watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset, .TEST); // check if PCW is stuck
ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM,
dut.core.ifu.PCM, InstrM, dut.core.lsu.IEUAdrM, InstrMName);
@ -716,13 +716,15 @@ module testbench;
always @(posedge clk) begin
// if (reset) PrevPCZero <= 0;
// else if (dut.core.InstrValidM) PrevPCZero <= (functionName.PCM == 0 & dut.core.ifu.InstrM == 0);
TestComplete <= ((InstrM == 32'h6f) & dut.core.InstrValidM ) |
((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"] & dut.core.lsu.IEUAdrM != 0) & InstrMName == "SW"); // |
// (functionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero));
// if (functionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero)
// $error("Program fetched illegal instruction 0x00000000 from address 0x00000000 twice in a row. Usually due to fault with no fault handler.");
if (reset) PrevPCZero <= 0;
else if (dut.core.InstrValidM) PrevPCZero <= (dut.core.PCM == 0 & dut.core.ifu.InstrM == 0);
if (dut.core.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero) begin
$error("Program fetched illegal instruction 0x00000000 from address 0x00000000 twice in a row. Usually due to fault with no fault handler.");
$fatal(1);
end
end
DCacheFlushFSM #(P) DCacheFlushFSM(.clk, .start(DCacheFlushStart), .done(DCacheFlushDone));
@ -766,7 +768,7 @@ end
string filename;
initial begin
// imperasDV requires the elffile be defined at the begining of the simulation.
// imperasDV requires the elffile be defined at the beginning of the simulation.
int iter;
longint x64;
int x32[2];

26
testbench/testbench_fp.sv
View file

@ -54,7 +54,7 @@ module testbench_fp;
logic [P.Q_LEN*4+7:0] TestVectors[MAXVECTORS-1:0]; // list of test vectors
logic [1:0] FmtVal; // value of the current Fmt
logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal
logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the current Unit/OpCtrl/FrmVal
logic WriteIntVal; // value of the current WriteInt
logic [P.Q_LEN-1:0] X, Y, Z; // inputs read from TestFloat
logic [P.FLEN-1:0] XPostBox; // inputs read from TestFloat
@ -67,7 +67,7 @@ module testbench_fp;
logic [P.FLEN-1:0] FpRes, FpCmpRes; // Results from each unit
logic [P.XLEN-1:0] IntRes, CmpRes; // Results from each unit
logic [P.Q_LEN-1:0] FpResExtended; // FpRes extended to same length as Ans/Res
logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags
logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputted flags
logic AnsNaN, ResNaN, NaNGood;
logic Xs, Ys, Zs; // sign of the inputs
logic [P.NE-1:0] Xe, Ye, Ze; // exponent of the inputs
@ -141,10 +141,10 @@ module testbench_fp;
///////////////////////////////////////////////////////////////////////////////////////////////
// select tests relevent to the specified configuration
// select tests relevant to the specified configuration
// cvtint - test integer conversion unit (fcvtint)
// cvtfp - test floating-point conversion unit (fcvtfp)
// cmp - test comparison unit's LT, LE, EQ opperations (fcmp)
// cmp - test comparison unit's LT, LE, EQ operations (fcmp)
// add - test addition
// sub - test subtraction
// div - test division
@ -157,7 +157,7 @@ module testbench_fp;
// $display("This simulation for TEST is %s", TEST);
// $display("This simulation for TEST is of the operand size of %s", TEST_SIZE);
if (P.Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad percision is supported
if (P.Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad precision is supported
if (TEST === "cvtint" | TEST === "all") begin // if testing integer conversion
// add the 128-bit cvtint tests to the to-be-tested list
Tests = {Tests, f128rv32cvtint};
@ -359,7 +359,7 @@ module testbench_fp;
end
end
end
if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested
if (TEST === "cmp" | TEST === "all") begin // if comparisons are being tested
// add the correct tests/op-ctrls/unit/fmt to their lists
Tests = {Tests, f64cmp};
OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
@ -470,7 +470,7 @@ module testbench_fp;
end
end
end
if (TEST === "cmp" | TEST === "all") begin // if comparision is being tested
if (TEST === "cmp" | TEST === "all") begin // if comparison is being tested
// add the correct tests/op-ctrls/unit/fmt to their lists
Tests = {Tests, f32cmp};
OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
@ -563,7 +563,7 @@ module testbench_fp;
end
end
end
if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested
if (TEST === "cmp" | TEST === "all") begin // if comparisons are being tested
// add the correct tests/op-ctrls/unit/fmt to their lists
Tests = {Tests, f16cmp};
OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
@ -904,8 +904,8 @@ module testbench_fp;
// check results on falling edge of clk
always @(negedge clk) begin
// check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify:
// - the sign of the NaN does not matter for the opperations being tested
// - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter
// - the sign of the NaN does not matter for the operations being tested
// - when 2 or more NaNs are inputted the NaN that is propagated doesn't matter
if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT)
case (FmtVal)
2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
@ -1275,7 +1275,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
`CVTINTUNIT:
case (Fmt)
2'b11: begin // quad
// {is the integer a long, is the opperation to an integer}
// {is the integer a long, is the operation to an integer}
casez ({OpCtrl[2:1]})
2'b11: begin // long -> quad
X = {P.Q_LEN{1'bx}};
@ -1327,7 +1327,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
endcase
end
2'b00: if (P.F_SUPPORTED) begin // single
// {is the integer a long, is the opperation to an integer}
// {is the integer a long, is the operation to an integer}
casez ({OpCtrl[2:1]})
2'b11: begin // long -> single
X = {P.Q_LEN{1'bx}};
@ -1353,7 +1353,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
endcase
end
2'b10: begin // half
// {is the integer a long, is the opperation to an integer}
// {is the integer a long, is the operation to an integer}
casez ({OpCtrl[2:1]})
2'b11: begin // long -> half
X = {P.Q_LEN{1'bx}};

6
testbench/tests.vh
View file

@ -94,7 +94,7 @@ string embench[] = '{
"bd_speedopt_speed/src/edn/edn",
"bd_speedopt_speed/src/huffbench/huffbench",
"bd_speedopt_speed/src/matmult-int/matmult-int",
"bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stabilty, add these tests back
"bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stably, add these tests back
"bd_speedopt_speed/src/minver/minver",
"bd_speedopt_speed/src/nettle-aes/nettle-aes",
"bd_speedopt_speed/src/nettle-sha256/nettle-sha256",
@ -1867,12 +1867,12 @@ string arch64d[] = '{
"rv64i_m/D/src/fssub.d_b8-01.S"
};
string arch64zicboz[] = '{ // as of 12/17/23 presently cbo.zero is the only CMO insturction with riscv-arch-test support
string arch64zicboz[] = '{ // as of 12/17/23 presently cbo.zero is the only CMO instruction with riscv-arch-test support
`RISCVARCHTEST,
"rv64i_m/CMO/src/cbo.zero-01.S"
};
string arch32zicboz[] = '{ // as of 12/17/23 presently cbo.zero is the only CMO insturction with riscv-arch-test support
string arch32zicboz[] = '{ // as of 12/17/23 presently cbo.zero is the only CMO instruction with riscv-arch-test support
`RISCVARCHTEST,
"rv32i_m/CMO/src/cbo.zero-01.S"
};

2
testbench/trek_files/trek_user_backdoor.sv
View file

@ -84,7 +84,7 @@ bit trek_is_event_addr;
// (`RAM_PATH.n_we == 1'b0));
//end
// Design specifc: one stage delayed so write has a time to settle
// Design specific: one stage delayed so write has a time to settle
//always @(posedge trek_c2t_mbox_event) begin: read_all_mailboxes
always @(posedge testbench.clk) begin: read_all_mailboxes
trek_poll_mbox();