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Fixed bug with fpga makefile.

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This commit is contained in:
Ross Thompson 2022-11-07 09:20:05 -06:00
parent 6fdd603ba1
commit fd1ef82310
1 changed files with 2 additions and 2 deletions
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4
fpga/generator/Makefile
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@ -2,7 +2,7 @@ dst := IP
# vcu118
#export XILINX_PART := xcvu9p-flga2104-2L-e
#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
#export FREQ := 30
#export board := vcu118
# vcu108
export XILINX_PART := xcvu095-ffva2104-2-e
@ -13,7 +13,7 @@ export board := vcu108
all: FPGA
FPGA: IP
vivado -mode batch -source wally.tcl 2>&1 | tee wally.log
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
IP: $(dst)/xlnx_proc_sys_reset.log \
$(dst)/xlnx_ddr4-$(board).log \