cvw/testbench
Vikram Krishna 1e3d39ba3c WIP: Fetch buffer PCF logic
Increment PCF one final time when fetch buffer goes high. Currently
breaks sims because it increments twice for some reason right now.

Co-authored-by: Jordan Carlin <jcarlin@hmc.edu>
Co-authered-by: Corey Hickson <chickson@hmc.edu>
2025-02-11 15:35:36 -08:00
..
common Merge branch 'main' of github.com:openhwgroup/cvw into fetch_buffer 2025-02-11 00:33:22 -08:00
sdc Lots more python updates 2024-12-17 21:31:12 -08:00
trek_files Update breker and enable interrupts 2025-01-30 00:58:53 -08:00
Makefile Add Makefile in testbench to allow the memfile to generate the correct version based on the elf output in objdump. Previously this was done via a findstring which works with riscv-arch-tests but doesn't allow individual programs/elf to be used unless the program is called xxx_rv32. 2025-01-24 08:55:25 -06:00
testbench.sv WIP: Fetch buffer PCF logic 2025-02-11 15:35:36 -08:00
testbench_fp.sv
tests.vh Update riscv-arch-test and enable remaining Zcf and Zcd tests 2025-01-17 10:32:28 -08:00
tests_fp.vh
wallywrapper.sv