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debug
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Added new tsm for debuggin the plic.
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2024-12-03 15:28:39 -06:00 |
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ahbaxibridge.tcl
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More updates to fpga IP module names.
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2024-08-22 14:31:39 -07:00 |
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clkconverter.tcl
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More updates to fpga IP module names.
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2024-08-22 14:31:39 -07:00 |
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ddr3-ArtyA7.tcl
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More updates to fpga IP module names.
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2024-08-22 14:31:39 -07:00 |
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ddr3-genesys2.tcl
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Holy smokes! first try and I got the genesys2 board running!
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2025-05-30 11:52:53 -07:00 |
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ddr4-vcu108.tcl
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This actually fixes the vcu108 to correctly set the SPI clock frequency.
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2024-09-03 13:11:03 -07:00 |
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ddr4-vcu118.tcl
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Fixed bugs in the fpga Makefile and vcu118 ddr memory gen script.
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2024-09-03 21:03:38 -07:00 |
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insert_debug_comment.sh
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Maded insert_debug_comment.sh compatible with cygwin.
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2024-04-22 10:48:34 -05:00 |
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Makefile
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Holy smokes! first try and I got the genesys2 board running!
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2025-05-30 11:52:53 -07:00 |
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mmcm-genesys2.tcl
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Holy smokes! first try and I got the genesys2 board running!
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2025-05-30 11:52:53 -07:00 |
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mmcm.tcl
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Finally worked out that subtle bug in the tcl scripts clock setting.
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2024-09-03 10:30:34 -07:00 |
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probe
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Fix new python lint errors discovered
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2025-04-08 20:53:33 -07:00 |
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sysrst.tcl
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More updates to fpga IP module names.
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2024-08-22 14:31:39 -07:00 |
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wally.tcl
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Holy smokes! first try and I got the genesys2 board running!
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2025-05-30 11:52:53 -07:00 |
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wave_config.wcfg
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remove hard-code path in wave_config.wcfg even though its probably not needed. Its a generated file. I believe the path doesn't matter, so I removed it.
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2024-09-18 15:40:00 -05:00 |
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xlnx_ddr3-artya7-mig.prj
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It's almost working.
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2023-04-18 14:24:59 -05:00 |
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xlnx_ddr3-genesys2-mig.prj
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Holy smokes! first try and I got the genesys2 board running!
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2025-05-30 11:52:53 -07:00 |
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xlnx_ddr4.tcl
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More updates to fpga IP module names.
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2024-08-22 14:31:39 -07:00 |
