cvw/fpga/constraints
2025-05-30 11:52:53 -07:00
..
artyddr3.ucf
big-debug-spi.xdc
constraints-ArtyA7.xdc
constraints-genesys2.xdc Holy smokes! first try and I got the genesys2 board running! 2025-05-30 11:52:53 -07:00
constraints-vcu108.xdc
constraints-vcu118.xdc
debug2.xdc
debug4.xdc
debug6.xdc Updated debug6, the large ila. 2025-05-05 19:15:45 -05:00
marked_debug.txt Added new debug scripts. 2024-12-03 12:17:10 -06:00
marked_debug_all.txt
marked_debug_debug6.txt Updated debug6, the large ila. 2025-05-05 19:15:45 -05:00
marked_debug_rvvi.txt
marked_debug_small.txt
marked_debug_spi.txt
marked_debug_uart.txt Added new debug scripts. 2024-12-03 12:17:10 -06:00
small-debug-rvvi.xdc
small-debug-spi.xdc
small-debug-uart.xdc Added new debug scripts. 2024-12-03 12:17:10 -06:00
small-debug-wfi.xdc Added new debug scripts. 2024-12-03 12:17:10 -06:00
small-debug.xdc
vcu-small-debug.xdc