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283 lines
16 KiB
Tcl
283 lines
16 KiB
Tcl
# The main clocks are all autogenerated by the Xilinx IP
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# clk_out3_xlnx_mmcm is the 20Mhz clock from the mmcm used to drive wally and the AHB Bus.
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# mmcm_clkout0 is the clock output of the DDR3 memory interface / 4.
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# This clock is not used by wally or the AHB Bus. However it is used by the AXI BUS on the DD3 IP.
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#create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
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create_generated_clock -name SPISDCClock -source [get_pins mmcm/clk_out3] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPICLK]
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##### clock #####
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set_property PACKAGE_PIN AD12 [get_ports default_200mhz_clk_p]
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set_property PACKAGE_PIN AD11 [get_ports default_200mhz_clk_n]
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set_property IOSTANDARD LVDS [get_ports default_200mhz_clk_p]
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# *** don't love this hack. RT: Don't understand why the recomemded input clock is causing a clock routing issue.
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set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets default_200mhz_clk_p]
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set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets default_200mhz_clk_n]
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##### RVVI Ethernet ####
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# taken from https://github.com/Digilent/digilent-xdc/blob/master/Genesys-2-Master.xdc
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set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS15 } [get_ports { phy_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl
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set_property -dict { PACKAGE_PIN AG10 IOSTANDARD LVCMOS15 } [get_ports { phy_rx_clk }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk
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set_property -dict { PACKAGE_PIN AJ14 IOSTANDARD LVCMOS15 } [get_ports { phy_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0]
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set_property -dict { PACKAGE_PIN AH14 IOSTANDARD LVCMOS15 } [get_ports { phy_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1]
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set_property -dict { PACKAGE_PIN AK13 IOSTANDARD LVCMOS15 } [get_ports { phy_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2]
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set_property -dict { PACKAGE_PIN AJ13 IOSTANDARD LVCMOS15 } [get_ports { phy_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3]
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set_property -dict { PACKAGE_PIN AE10 IOSTANDARD LVCMOS15 } [get_ports { phy_tx_clk }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
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set_property -dict { PACKAGE_PIN AK14 IOSTANDARD LVCMOS15 } [get_ports { phy_tx_en }]; #IO_L20P_T3_33 Sch=eth_tx_en
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set_property -dict { PACKAGE_PIN AJ12 IOSTANDARD LVCMOS15 } [get_ports { phy_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0]
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set_property -dict { PACKAGE_PIN AK11 IOSTANDARD LVCMOS15 } [get_ports { phy_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1]
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set_property -dict { PACKAGE_PIN AJ11 IOSTANDARD LVCMOS15 } [get_ports { phy_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2]
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set_property -dict { PACKAGE_PIN AK10 IOSTANDARD LVCMOS15 } [get_ports { phy_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3]
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# have to update these in the future. Follow the rvviopt branch from the vcu108 config.
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#set_property -dict { PACKAGE_PIN AK16 IOSTANDARD LVCMOS18 } [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
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#set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS15 } [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc
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#set_property -dict { PACKAGE_PIN AG12 IOSTANDARD LVCMOS15 } [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio
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#set_property -dict { PACKAGE_PIN AH24 IOSTANDARD LVCMOS33 } [get_ports { ETH_PHYRST_N }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n
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#set_property -dict { PACKAGE_PIN AK15 IOSTANDARD LVCMOS18 } [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
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##### GPI ####
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set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS12 } [get_ports { GPI[0] }]; #IO_25_17 Sch=btnc
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set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS12 } [get_ports { GPI[1] }]; #IO_0_15 Sch=btnd
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set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS12 } [get_ports { GPI[2] }]; #IO_L6P_T0_15 Sch=btnl
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set_property -dict { PACKAGE_PIN C19 IOSTANDARD LVCMOS12 } [get_ports { GPI[3] }]; #IO_L24P_T3_17 Sch=btnr
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set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPI[*]}]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports {GPI[*]}]
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set_max_delay -from [get_ports {GPI[*]}] 20.000
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##### GPO ####
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set_property -dict { PACKAGE_PIN T28 IOSTANDARD LVCMOS33 } [get_ports { GPO[0] }]; #IO_L11N_T1_SRCC_14 Sch=led[0]
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set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { GPO[1] }]; #IO_L19P_T3_A10_D26_14 Sch=led[1]
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set_property -dict { PACKAGE_PIN U30 IOSTANDARD LVCMOS33 } [get_ports { GPO[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[2]
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set_property -dict { PACKAGE_PIN U29 IOSTANDARD LVCMOS33 } [get_ports { GPO[3] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=led[3]
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set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { GPO[4] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=led[4]
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set_max_delay -to [get_ports {GPO[*]}] 20.000
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set_output_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
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set_output_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}]
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##### UART #####
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# *** IOSTANDARD is probably wrong
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set_property -dict { PACKAGE_PIN Y23 IOSTANDARD LVCMOS33 } [get_ports { UARTSout }]; #IO_L1P_T0_12 Sch=uart_rx_out
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set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { UARTSin }]; #IO_0_12 Sch=uart_tx_in
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#set_property DRIVE 4 [get_ports UARTSout]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSin]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports UARTSin]
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set_output_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
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set_output_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports UARTSout]
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##### reset #####
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#************** reset is inverted
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set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS12 } [get_ports { south_reset }]; #IO_L24N_T3_17 Sch=btnu
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set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { resetn }]; #IO_0_14 Sch=cpu_resetn
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set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 2.000 [get_ports resetn]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 2.000 [get_ports resetn]
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set_max_delay -from [get_ports resetn] 20.000
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set_false_path -from [get_ports resetn]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 2.000 [get_ports south_reset]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 2.000 [get_ports south_reset]
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set_max_delay -from [get_ports south_reset] 20.000
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set_false_path -from [get_ports south_reset]
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##### SD Card I/O #####
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#***** may have to switch to Pmod JB or JC.
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# SDCDat[3]
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set_property PACKAGE_PIN V27 [get_ports SDCCS]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCS]
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set_property PULLTYPE PULLUP [get_ports SDCCS]
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# set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[2]}]
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# set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[1]}]
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# SDCDat[0]
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set_property PACKAGE_PIN V24 [get_ports SDCIn]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCIn]
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set_property PULLTYPE PULLUP [get_ports SDCIn]
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set_property PACKAGE_PIN W22 [get_ports SDCCLK]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK]
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set_property PULLTYPE PULLUP [get_ports SDCCLK]
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set_property PACKAGE_PIN Y30 [get_ports SDCCmd]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCmd]
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set_property PULLTYPE PULLUP [get_ports SDCCmd]
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set_property PACKAGE_PIN V22 [get_ports SDCCD]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCD]
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set_property PULLTYPE PULLUP [get_ports SDCCD]
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set_property PACKAGE_PIN W21 [get_ports SDCWP]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCWP]
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set_property PULLTYPE PULLUP [get_ports SDCWP]
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set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
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set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}]
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set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}]
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set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}]
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set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks SPISDCClock] 0.000 [get_ports SDCCLK]
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#set_multicycle_path -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10
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set_max_delay -datapath_only -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 20.000
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# *********************************
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#set_property DCI_CASCADE {64} [get_iobanks 65]
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#set_property INTERNAL_VREF 0.9 [get_iobanks 65]
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# ddr3
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[16]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[17]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[18]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[19]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[20]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[21]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[22]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[23]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[24]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[25]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[26]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[27]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[28]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[29]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[30]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[31]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}]
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set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr3_dqs_p[0]]
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set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr3_dqs_n[0]]
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set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr3_dqs_p[1]]
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set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr3_dqs_n[1]]
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set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr3_dqs_p[2]]
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set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr3_dqs_n[2]]
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set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr3_dqs_p[3]]
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set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr3_dqs_n[3]]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]
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set_property IOSTANDARD DIFF_SSTL15_DCI [get_ports ddr3_ck_p[0]]
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set_property IOSTANDARD DIFF_SSTL15_DCI [get_ports ddr3_ck_n[0]]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_ras_n]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_cas_n]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_we_n]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_reset_n]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n[0]}]
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set_property PACKAGE_PIN AC12 [get_ports ddr3_addr[0]]
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set_property PACKAGE_PIN AB8 [get_ports ddr3_addr[10]]
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set_property PACKAGE_PIN AA8 [get_ports ddr3_addr[11]]
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set_property PACKAGE_PIN AB12 [get_ports ddr3_addr[12]]
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set_property PACKAGE_PIN AA12 [get_ports ddr3_addr[13]]
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set_property PACKAGE_PIN AH9 [get_ports ddr3_addr[14]]
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set_property PACKAGE_PIN AE8 [get_ports ddr3_addr[1]]
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set_property PACKAGE_PIN AD8 [get_ports ddr3_addr[2]]
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set_property PACKAGE_PIN AC10 [get_ports ddr3_addr[3]]
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set_property PACKAGE_PIN AD9 [get_ports ddr3_addr[4]]
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set_property PACKAGE_PIN AA13 [get_ports ddr3_addr[5]]
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set_property PACKAGE_PIN AA10 [get_ports ddr3_addr[6]]
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set_property PACKAGE_PIN AA11 [get_ports ddr3_addr[7]]
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set_property PACKAGE_PIN Y10 [get_ports ddr3_addr[8]]
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set_property PACKAGE_PIN Y11 [get_ports ddr3_addr[9]]
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set_property PACKAGE_PIN AE9 [get_ports ddr3_ba[0]]
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set_property PACKAGE_PIN AB10 [get_ports ddr3_ba[1]]
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set_property PACKAGE_PIN AC11 [get_ports ddr3_ba[2]]
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set_property PACKAGE_PIN AF11 [get_ports ddr3_cas_n]
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set_property PACKAGE_PIN AC9 [get_ports ddr3_ck_n[0]]
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set_property PACKAGE_PIN AB9 [get_ports ddr3_ck_p[0]]
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set_property PACKAGE_PIN AJ9 [get_ports ddr3_cke[0]]
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set_property PACKAGE_PIN AH12 [get_ports ddr3_cs_n[0]]
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set_property PACKAGE_PIN AD4 [get_ports ddr3_dm[0]]
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set_property PACKAGE_PIN AF3 [get_ports ddr3_dm[1]]
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set_property PACKAGE_PIN AH4 [get_ports ddr3_dm[2]]
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set_property PACKAGE_PIN AF8 [get_ports ddr3_dm[3]]
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set_property PACKAGE_PIN AD3 [get_ports ddr3_dq[0]]
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set_property PACKAGE_PIN AF1 [get_ports ddr3_dq[10]]
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set_property PACKAGE_PIN AE4 [get_ports ddr3_dq[11]]
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set_property PACKAGE_PIN AE3 [get_ports ddr3_dq[12]]
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set_property PACKAGE_PIN AE5 [get_ports ddr3_dq[13]]
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set_property PACKAGE_PIN AF5 [get_ports ddr3_dq[14]]
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set_property PACKAGE_PIN AF6 [get_ports ddr3_dq[15]]
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set_property PACKAGE_PIN AJ4 [get_ports ddr3_dq[16]]
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set_property PACKAGE_PIN AH6 [get_ports ddr3_dq[17]]
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set_property PACKAGE_PIN AH5 [get_ports ddr3_dq[18]]
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set_property PACKAGE_PIN AH2 [get_ports ddr3_dq[19]]
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set_property PACKAGE_PIN AC2 [get_ports ddr3_dq[1]]
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set_property PACKAGE_PIN AJ2 [get_ports ddr3_dq[20]]
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set_property PACKAGE_PIN AJ1 [get_ports ddr3_dq[21]]
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set_property PACKAGE_PIN AK1 [get_ports ddr3_dq[22]]
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set_property PACKAGE_PIN AJ3 [get_ports ddr3_dq[23]]
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set_property PACKAGE_PIN AF7 [get_ports ddr3_dq[24]]
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set_property PACKAGE_PIN AG7 [get_ports ddr3_dq[25]]
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set_property PACKAGE_PIN AJ6 [get_ports ddr3_dq[26]]
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set_property PACKAGE_PIN AK6 [get_ports ddr3_dq[27]]
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set_property PACKAGE_PIN AJ8 [get_ports ddr3_dq[28]]
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set_property PACKAGE_PIN AK8 [get_ports ddr3_dq[29]]
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set_property PACKAGE_PIN AC1 [get_ports ddr3_dq[2]]
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set_property PACKAGE_PIN AK5 [get_ports ddr3_dq[30]]
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set_property PACKAGE_PIN AK4 [get_ports ddr3_dq[31]]
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set_property PACKAGE_PIN AC5 [get_ports ddr3_dq[3]]
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set_property PACKAGE_PIN AC4 [get_ports ddr3_dq[4]]
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set_property PACKAGE_PIN AD6 [get_ports ddr3_dq[5]]
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set_property PACKAGE_PIN AE6 [get_ports ddr3_dq[6]]
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set_property PACKAGE_PIN AC7 [get_ports ddr3_dq[7]]
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set_property PACKAGE_PIN AF2 [get_ports ddr3_dq[8]]
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set_property PACKAGE_PIN AE1 [get_ports ddr3_dq[9]]
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set_property PACKAGE_PIN AD1 [get_ports ddr3_dqs_n[0]]
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set_property PACKAGE_PIN AG3 [get_ports ddr3_dqs_n[1]]
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set_property PACKAGE_PIN AH1 [get_ports ddr3_dqs_n[2]]
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set_property PACKAGE_PIN AJ7 [get_ports ddr3_dqs_n[3]]
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set_property PACKAGE_PIN AD2 [get_ports ddr3_dqs_p[0]]
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set_property PACKAGE_PIN AG4 [get_ports ddr3_dqs_p[1]]
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set_property PACKAGE_PIN AG2 [get_ports ddr3_dqs_p[2]]
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set_property PACKAGE_PIN AH7 [get_ports ddr3_dqs_p[3]]
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set_property PACKAGE_PIN AK9 [get_ports ddr3_odt[0]]
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set_property PACKAGE_PIN AE11 [get_ports ddr3_ras_n]
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set_property PACKAGE_PIN AG5 [get_ports ddr3_reset_n]
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set_property PACKAGE_PIN AG13 [get_ports ddr3_we_n]
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