cvw/examples/exercises/fma16/synthDC
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Makefile fma synthesis and test vectors 2025-04-21 06:25:27 -07:00
README.md Updated README 2025-04-22 16:27:21 -07:00

Synthesis

This subdirectory contains synthesis scripts for use with Synopsys (snps) Design Compiler (DC). Synthesis commands are found in scripts/synth.tcl.

Example Usage

make synth FREQ=500 

Environment Variables

  • FREQ
    • Frequency in MHz. Default is 500
    • The target standard cell library. The default is sky130.
  • TECH
    • Options:
    • sky90: skywater 90nm TT 25C
    • sky130: skywater 130nm TT 25C
  • SAIFPOWER
    • Controls if power analysis is driven by switching factor or RTL modelsim simulation. When enabled requires a saif file named power.saif. The default is 0.
    • Options:
      • 0: switching factor power analysis
      • 1: RTL simulation driven power analysis.