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Cleanup; removed carry and overflow (mostly)
This commit is contained in:
Sven Stucki
parent
509c13dff8
commit
186245bc49
4 changed files with 9 additions and 84 deletions
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@ -116,9 +116,7 @@ module controller
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input logic dbg_set_npc_i, // Change PC to value from debug unit
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output logic dbg_trap_o, // trap hit, inform debug unit
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// SPR Signals
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output logic set_carry_o, // to special purpose registers --> carry
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output logic set_overflow_o, // to special purpose registers --> overflow
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// CSR Signals
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output logic restore_sr_o, // restores status register after interrupt
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// Forwarding signals from regfile
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@ -161,8 +159,6 @@ module controller
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logic regfile_alu_we;
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logic data_we;
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logic data_req;
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logic set_overflow;
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logic set_carry;
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logic deassert_we;
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logic lsu_stall;
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@ -243,9 +239,6 @@ module controller
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data_reg_offset_o = 2'b00;
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data_req = 1'b0;
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set_overflow = 1'b0;
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set_carry = 1'b0;
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restore_sr_o = 1'b0;
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clear_isr_running_o = 1'b0;
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@ -1158,8 +1151,6 @@ module controller
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assign regfile_alu_we_o = (deassert_we) ? 1'b0 : regfile_alu_we;
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assign data_we_o = (deassert_we) ? 1'b0 : data_we;
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assign data_req_o = (deassert_we) ? 1'b0 : data_req;
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assign set_overflow_o = (deassert_we) ? 1'b0 : set_overflow;
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assign set_carry_o = (deassert_we) ? 1'b0 : set_carry;
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////////////////////////////////////////////////////////////////////////////////////////////
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39
ex_stage.sv
39
ex_stage.sv
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@ -48,7 +48,6 @@ module ex_stage
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input logic [31:0] alu_operand_a_i,
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input logic [31:0] alu_operand_b_i,
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input logic [31:0] alu_operand_c_i,
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input logic alu_carry_i,
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input logic [1:0] vector_mode_i,
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input logic [1:0] alu_cmp_mode_i,
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@ -83,21 +82,11 @@ module ex_stage
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input logic [31:0] hwloop_pc_plus4_i,
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input logic [31:0] hwloop_cnt_i,
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input logic set_overflow_i,
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input logic set_carry_i,
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// CSR access
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input logic csr_access_i,
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input logic [31:0] csr_rdata_i,
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// Output of EX stage pipeline
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output logic carry_o,
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output logic overflow_o,
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output logic set_overflow_o,
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output logic set_carry_o,
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output logic [4:0] regfile_waddr_wb_o,
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output logic regfile_wdata_mux_sel_wb_o,
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output logic regfile_we_wb_o,
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@ -123,24 +112,14 @@ module ex_stage
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);
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// Alu outputs - OVerflow and CarrY
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logic alu_overflow_int;
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logic alu_carry_int;
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// Internal output of the LU
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logic [31:0] alu_result;
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logic [31:0] alu_adder_lsu_int; // to LS unit
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logic [31:0] mult_result;
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logic mult_carry_int;
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logic mult_overflow_int;
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// Result Selection: Select between ALU output signals and MUL
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assign carry_o = (mult_en_i == 1'b1) ? mult_carry_int : alu_carry_int;
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assign overflow_o = (mult_en_i == 1'b1) ? mult_overflow_int : alu_overflow_int;
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assign regfile_alu_we_fw_o = regfile_alu_we_i;
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assign regfile_alu_waddr_fw_o = regfile_alu_waddr_i;
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@ -156,10 +135,6 @@ module ex_stage
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end
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// assign regfile_alu_wdata_fw_o = (mult_en_i == 1'b0) ? alu_result : mult_result;
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// generate flags: goes to special purpose register
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assign set_overflow_o = (stall_ex_i == 1'b0) ? set_overflow_i : 1'b0;
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assign set_carry_o = (stall_ex_i == 1'b0) ? set_carry_i : 1'b0;
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//NOTE Igor fix: replaced alu_adder_int with alu_adder_lsu_int --> Now data_addr is calculated with
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//NOTE a dedicated adder, no carry is considered , just op_a + op_b from id stage
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assign data_addr_ex_o = (prepost_useincr_i == 1'b1) ? alu_adder_lsu_int : alu_operand_a_i;
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@ -198,7 +173,8 @@ module ex_stage
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.operand_a_i ( alu_operand_a_i ),
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.operand_b_i ( alu_operand_b_i ),
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.operand_c_i ( alu_operand_c_i ),
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.carry_i ( alu_carry_i ),
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.carry_i ( 1'b0 ),
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.flag_i ( 1'b0 ),
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.vector_mode_i ( vector_mode_i ),
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.cmp_mode_i ( alu_cmp_mode_i ),
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@ -207,8 +183,9 @@ module ex_stage
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.adder_lsu_o ( alu_adder_lsu_int ),
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.result_o ( alu_result ),
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.overflow_o ( alu_overflow_int ),
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.carry_o ( alu_carry_int )
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.overflow_o ( ),
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.carry_o ( ),
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.flag_o ( )
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);
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@ -231,12 +208,12 @@ module ex_stage
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.op_a_i ( alu_operand_a_i ),
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.op_b_i ( alu_operand_b_i ),
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.mac_i ( alu_operand_c_i ),
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.carry_i ( alu_carry_i ),
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.carry_i ( 1'b0 ),
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.result_o ( mult_result ),
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.carry_o ( mult_carry_int ),
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.overflow_o ( mult_overflow_int )
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.carry_o ( ),
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.overflow_o ( )
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);
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16
id_stage.sv
16
id_stage.sv
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@ -115,10 +115,6 @@ module id_stage
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input logic data_ack_i, // Grant from data memory
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input logic data_rvalid_i,
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// SPR signals
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output logic set_carry_ex_o,
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output logic set_overflow_ex_o,
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// Interrupt signals
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input logic irq_i,
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input logic irq_nm_i,
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@ -262,10 +258,6 @@ module id_stage
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logic csr_access;
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logic [1:0] csr_op;
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// Supervision Register
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logic set_carry;
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logic set_overflow;
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logic prepost_useincr;
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// Forwarding
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@ -633,8 +625,6 @@ module id_stage
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.dbg_trap_o ( dbg_trap_o ),
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// SPR Signals
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.set_overflow_o ( set_overflow ),
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.set_carry_o ( set_carry ),
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.restore_sr_o ( restore_sr_o ),
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// regfile port 1
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@ -803,9 +793,6 @@ module id_stage
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data_misaligned_ex_o <= 1'b0;
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set_overflow_ex_o <= 1'b0;
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set_carry_ex_o <= 1'b0;
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hwloop_we_ex_o <= 3'b0;
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hwloop_regid_ex_o <= 2'b0;
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hwloop_wb_mux_sel_ex_o <= 1'b0;
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@ -875,9 +862,6 @@ module id_stage
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data_misaligned_ex_o <= 1'b0;
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set_overflow_ex_o <= set_overflow;
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set_carry_ex_o <= set_carry;
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hwloop_we_ex_o <= hwloop_we;
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hwloop_regid_ex_o <= hwloop_regid;
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hwloop_wb_mux_sel_ex_o <= hwloop_wb_mux_sel;
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@ -121,10 +121,6 @@ module riscv_core
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logic [1:0] alu_cmp_mode_ex;
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logic [1:0] alu_vec_ext_ex;
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// Result Control
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logic carry_ex;
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logic overflow_ex;
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// Multiplier Control
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logic mult_en_ex;
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logic [1:0] mult_sel_subword_ex;
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@ -170,15 +166,6 @@ module riscv_core
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logic [31:0] lsu_data_reg;
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logic data_ack_int;
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// Supervision Register
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logic set_carry_ex;
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logic set_overflow_ex;
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logic set_carry_fw_ex;
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logic set_overflow_fw_ex;
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// Direct Supervision-Register access
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logic carry_sp;
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// Signals between instruction core interface and pipe (if and id stages)
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logic [31:0] instr_rdata_int; // read instruction from the instruction core interface to if_stage
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logic instr_req_int; // Id stage asserts a req to instruction core interface
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@ -430,9 +417,6 @@ module riscv_core
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.data_ack_i ( data_ack_int ), // from load store unit
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.data_rvalid_i ( data_r_valid_i ),
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.set_carry_ex_o ( set_carry_ex ), // to ex_stage
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.set_overflow_ex_o ( set_overflow_ex ), // to ex_stage
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// Interrupt Signals
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.irq_i ( irq_i ), // incoming interrupts
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.irq_nm_i ( irq_nm_i ), // incoming interrupts
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@ -495,7 +479,6 @@ module riscv_core
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.alu_operand_a_i ( alu_operand_a_ex ), // from ID/EX pipe registers
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.alu_operand_b_i ( alu_operand_b_ex ), // from ID/EX pipe registers
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.alu_operand_c_i ( alu_operand_c_ex ), // from ID/EX pipe registers
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.alu_carry_i ( carry_sp ), // from spr carry
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.vector_mode_i ( vector_mode_ex ), // from ID/EX pipe registers
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.alu_cmp_mode_i ( alu_cmp_mode_ex ), // from ID/EX pipe registers
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@ -508,13 +491,6 @@ module riscv_core
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.mult_use_carry_i ( mult_use_carry_ex ),
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.mult_mac_en_i ( mult_mac_en_ex ),
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/*
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// interface with Special registers
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.carry_o ( carry_ex ),
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.overflow_o ( overflow_ex ),
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.set_overflow_o ( set_overflow_fw_ex ), // to special registers
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.set_carry_o ( set_carry_fw_ex ), // to special registers
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*/
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// interface with CSRs
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.csr_access_i ( csr_access_ex ),
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.csr_rdata_i ( csr_rdata ),
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@ -539,9 +515,6 @@ module riscv_core
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.hwloop_cnt_i ( hwlp_cnt_ex ),
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//From ID stage.Controller
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.set_overflow_i ( set_overflow_ex ),
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.set_carry_i ( set_carry_ex ),
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.regfile_rb_data_i ( regfile_rb_data_ex ),
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// Output of ex stage pipeline
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