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include
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Another compressed instruction, include guards for verilator
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2015-07-21 17:57:49 +02:00 |
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alu.sv
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Realigned RiscV with Or10n, code cleanup
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2015-05-24 23:04:36 +02:00 |
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compressed_decoder.sv
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Another compressed instruction, include guards for verilator
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2015-07-21 17:57:49 +02:00 |
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controller.sv
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Cleanup; removed carry and overflow (mostly)
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2015-07-23 01:20:57 +02:00 |
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cs_registers.sv
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Fixed inferred latches in RV
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2015-06-05 12:23:35 +02:00 |
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debug_unit.sv
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Initial RiscV core commit; still in an early stage, but ALU instructions work
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2015-04-01 11:11:07 +02:00 |
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ex_stage.sv
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Cleanup; removed carry and overflow (mostly)
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2015-07-23 01:20:57 +02:00 |
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exc_controller.sv
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RiscV: exception controller and CSR core and synthesis update
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2015-05-26 00:08:44 +02:00 |
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id_stage.sv
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Cleanup; removed carry and overflow (mostly)
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2015-07-23 01:20:57 +02:00 |
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if_stage.sv
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Major RiscV update, now supports compressed instructions (partially, work-in-progress until full standard is released)
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2015-06-12 19:26:16 +02:00 |
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instr_core_interface.sv
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Fixed space/tab mixture and indentation in instr_core_interface
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2015-04-16 15:21:03 +02:00 |
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load_store_unit.sv
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Initial RiscV core commit; still in an early stage, but ALU instructions work
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2015-04-01 11:11:07 +02:00 |
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mult.sv
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Realigned RiscV with Or10n, code cleanup
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2015-05-24 23:04:36 +02:00 |
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register_file.sv
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Initial RiscV core commit; still in an early stage, but ALU instructions work
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2015-04-01 11:11:07 +02:00 |
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riscv_core.sv
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Cleanup; removed carry and overflow (mostly)
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2015-07-23 01:20:57 +02:00 |
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wb_stage.sv
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Fixed inferred latches in RV
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2015-06-05 12:23:35 +02:00 |
