mirror of
https://github.com/lowRISC/ibex.git
synced 2025-04-22 04:47:25 -04:00
Merge branch 'rvc18'
Adds support for the updated RVC extension. The spec is not final yet, but the compiler already supports and uses it. This update makes it possible to use the most up-to-date compiler version.
This commit is contained in:
Sven Stucki
commit
3a992372d6
1 changed files with 32 additions and 131 deletions
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@ -52,26 +52,28 @@ module compressed_decoder
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unique case (instr_i[15:13])
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3'b000: begin
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if (instr_i[12] == 1'b0) begin
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// c.mv -> add rd, x0, rs2
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// c.mv -> add rd/rs1, x0, rs2
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instr_o = {7'b0, instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], `OPCODE_OP};
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if (instr_i[6:2] == 5'b0) begin
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// c.jr -> jalr x0, rd/rs1, 0
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instr_o = {12'b0, instr_i[11:7], 3'b0, 5'b0, `OPCODE_JALR};
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end
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end else begin
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// c.add -> add rd, rd, rs2
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instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b000, instr_i[11:7], `OPCODE_OP};
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end
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if (instr_i[11:7] == 5'b0) begin
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if (instr_i[6:2] == 5'b0)
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instr_o = {32'h00_10_00_73}; // EBREAK
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else
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illegal_instr_o = 1'b1;
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end
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end
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3'b001: begin
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// c.srai -> srai rd, rd, shamt
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instr_o = {2'b01, 5'b0, instr_i[6:2], instr_i[11:7], 3'b101, instr_i[11:7], `OPCODE_OPIMM};
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if (instr_i[12] != 1'b0) illegal_instr_o = 1'b1;
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if (instr_i[6:2] == 5'b0) illegal_instr_o = 1'b1;
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if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
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if (instr_i[11:7] == 5'b0) begin
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// c.ebreak -> ebreak
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instr_o = {32'h00_10_00_73};
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if (instr_i[6:2] != 5'b0)
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illegal_instr_o = 1'b1;
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end else if (instr_i[6:2] == 5'b0) begin
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// c.jalr -> jalr x1, rs1, 0
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instr_o = {12'b0, instr_i[11:7], 3'b000, 5'b00001, `OPCODE_JALR};
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end
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end
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end
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3'b010: begin
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@ -79,57 +81,9 @@ module compressed_decoder
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instr_o = {5'b0, instr_i[5], instr_i[12], 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6], 2'b00, `OPCODE_STORE};
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end
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3'b011: begin
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instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b0, 2'b01, instr_i[9:7], `OPCODE_OP};
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unique case ({instr_i[12:10], instr_i[6:5]})
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// c.xor -> xor rd', rd', rs2'
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5'b00000: instr_o = {7'b000_0000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b100, 2'b01, instr_i[9:7], `OPCODE_OP};
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// c.sll -> sll rd', rd', rs2'
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5'b00100: instr_o = {7'b000_0000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b001, 2'b01, instr_i[9:7], `OPCODE_OP};
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// c.srl -> srl rd', rd', rs2'
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5'b00101: instr_o = {7'b000_0000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b101, 2'b01, instr_i[9:7], `OPCODE_OP};
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// c.sra -> sra rd', rd', rs2'
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5'b00001: instr_o = {7'b010_0000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b101, 2'b01, instr_i[9:7], `OPCODE_OP};
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// c.sltu -> sltu rd', rd', rs2'
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5'b00111: instr_o = {7'b000_0000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b011, 2'b01, instr_i[9:7], `OPCODE_OP};
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// c.sllr -> sll rd', rs1', rd'
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5'b01100: instr_o = {7'b000_0000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b001, 2'b01, instr_i[4:2], `OPCODE_OP};
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// c.srlr -> srl rd', rs1', rd'
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5'b01101: instr_o = {7'b000_0000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b101, 2'b01, instr_i[4:2], `OPCODE_OP};
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// c.sltur -> sltu rd', rs1', rd'
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5'b01111: instr_o = {7'b000_0000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b011, 2'b01, instr_i[4:2], `OPCODE_OP};
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// c.slt -> slt rd', rd', rs2'
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5'b00110: instr_o = {7'b000_0000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[9:7], `OPCODE_OP};
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// c.sltr -> slt rd', rs1', rd'
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5'b01110: instr_o = {7'b000_0000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], `OPCODE_OP};
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default: illegal_instr_o = 1'b1;
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endcase
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end
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3'b100: begin
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// c.sub -> sub rd, rd rs2
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instr_o = {2'b01, 5'b0, instr_i[6:2], instr_i[11:7], 3'b000, instr_i[11:7], `OPCODE_OP};
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if (instr_i[12] != 1'b0) illegal_instr_o = 1'b1;
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if (instr_i[6:2] == 5'b0) illegal_instr_o = 1'b1;
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if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
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end
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3'b101: begin
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unique case (instr_i[6:5])
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// c.add3 -> add rd', rs1', rs2'
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2'b00: instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[12:10], `OPCODE_OP};
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// c.sub3 -> sub rd', rs1', rs2'
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2'b01: instr_o = {2'b01, 5'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[12:10], `OPCODE_OP};
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// c.or3 -> or rd'1, rs1', rs2'
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2'b10: instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b110, 2'b01, instr_i[12:10], `OPCODE_OP};
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// c.and3 -> and rd', rs1', rs2'
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2'b11: instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[12:10], `OPCODE_OP};
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endcase
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// c.addi4spn -> addi rd', x2, imm
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instr_o = {2'b0, instr_i[10:7], instr_i[12:11], instr_i[5], instr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], `OPCODE_OPIMM};
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end
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3'b110: begin
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@ -153,54 +107,17 @@ module compressed_decoder
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if (instr_i[12] == 1'b1 || instr_i[6:2] == 5'b0) illegal_instr_o = 1'b1;
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end
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3'b001: begin
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// c.srli -> srli rd, rd, shamt
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instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b101, instr_i[11:7], `OPCODE_OPIMM};
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if (instr_i[12] == 1'b1) illegal_instr_o = 1'b1;
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if (instr_i[6:2] == 5'b0) illegal_instr_o = 1'b1;
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if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
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end
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3'b010: begin
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// c.swsp -> sw rs2, imm(x2)
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instr_o = {4'b0, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010, instr_i[11:9], 2'b00, `OPCODE_STORE};
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end
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3'b011: begin
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// c.bltz -> blt rs1', x0, imm
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instr_o = {{3 {instr_i[12]}}, instr_i[12:10], instr_i[2], 5'b0, 2'b01, instr_i[9:7], 3'b100, instr_i[6:3], instr_i[12], `OPCODE_BRANCH};
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end
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3'b100: begin
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unique case (instr_i[6:5])
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// c.addin -> addi rd', rs1', imm
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2'b00: instr_o = {{9 {instr_i[12]}}, instr_i[12:10], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[4:2], `OPCODE_OPIMM};
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// c.xorin -> xori rd', rs1', imm
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2'b01: instr_o = {{9 {instr_i[12]}}, instr_i[12:10], 2'b01, instr_i[9:7], 3'b100, 2'b01, instr_i[4:2], `OPCODE_OPIMM};
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// c.orin -> ori rd', rs1', imm
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2'b10: instr_o = {{9 {instr_i[12]}}, instr_i[12:10], 2'b01, instr_i[9:7], 3'b110, 2'b01, instr_i[4:2], `OPCODE_OPIMM};
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// c.andin -> andi rd', rs1', imm
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2'b11: instr_o = {{9 {instr_i[12]}}, instr_i[12:10], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[4:2], `OPCODE_OPIMM};
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endcase
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if (instr_i[12:10] == 3'b0) illegal_instr_o = 1'b1;
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end
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3'b101: begin
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// c.addi4spn -> addi rd', x2, imm
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instr_o = {2'b0, instr_i[10:7], instr_i[12:11], instr_i[5], instr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], `OPCODE_OPIMM};
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end
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3'b110: begin
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// c.lwsp -> lw rd, imm(x2)
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instr_o = {4'b0, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02, 3'b010, instr_i[11:7], `OPCODE_LOAD};
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if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
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end
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3'b111: begin
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// c.bgez -> bge rs1', x0, imm
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instr_o = {{3 {instr_i[12]}}, instr_i[12:10], instr_i[2], 5'b0, 2'b01, instr_i[9:7], 3'b101, instr_i[6:3], instr_i[12], `OPCODE_BRANCH};
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end
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default: begin
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illegal_instr_o = 1'b1;
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end
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@ -223,44 +140,28 @@ module compressed_decoder
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end
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3'b100: begin
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if ({instr_i[12], instr_i[6:2]} == 6'b0) begin
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// c.jr -> jalr x0, rs1, 0
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instr_o = {12'b0, instr_i[11:7], 3'b0, 5'b0, `OPCODE_JALR};
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end else begin
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// c.li -> addi rd, x0, nzimm
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instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], `OPCODE_OPIMM};
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end
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// c.li -> addi rd, x0, nzimm
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instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], `OPCODE_OPIMM};
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if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
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end
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3'b101: begin
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if ({instr_i[12], instr_i[6:2]} == 6'b0) begin
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// c.jalr -> jalr x1, rs1, 0
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instr_o = {12'b0, instr_i[11:7], 3'b000, 5'b00001, `OPCODE_JALR};
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end else begin
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// c.lui -> lui rd, imm
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instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], `OPCODE_LUI};
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// c.lui -> lui rd, imm
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instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], `OPCODE_LUI};
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if (instr_i[11:7] == 5'b0) begin
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// c.addi16sp -> addi x2, x2, nzimm
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instr_o = {{3 {instr_i[12]}}, instr_i[4:2], instr_i[5], instr_i[6], 4'b0, 5'h02, 3'b000, 5'h02, `OPCODE_OPIMM};
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end
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if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
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if ({instr_i[12], instr_i[6:2]} == 6'b0) illegal_instr_o = 1'b1;
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end
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3'b110: begin
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if (instr_i[11:7] == 5'b0) begin
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// c.addi16sp -> addi x2, x2, nzimm
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// c.nop
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instr_o = {{3 {instr_i[12]}}, instr_i[4:2], instr_i[5], instr_i[6], 4'b0, 5'h02, 3'b000, 5'h02, `OPCODE_OPIMM};
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end else begin
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// c.addi -> addi rd, rd, nzimm
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instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], `OPCODE_OPIMM};
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if ({instr_i[12], instr_i[6:2]} == 6'b0) illegal_instr_o = 1'b1;
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end
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end
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3'b111: begin
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// c.andi -> andi rd, rd, nzimm
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instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], instr_i[11:7], 3'b111, instr_i[11:7], `OPCODE_OPIMM};
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if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
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// c.addi -> addi rd, rd, nzimm
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// c.nop
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instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], `OPCODE_OPIMM};
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end
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default: begin
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