Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

cpucorehardwarerisc-vrv32

Sven Stucki 3a992372d6 Merge branch 'rvc18' ... Adds support for the updated RVC extension. The spec is not final yet, but the compiler already supports and uses it. This update makes it possible to use the most up-to-date compiler version.		2015-09-25 13:19:41 +02:00
docs/datasheet	Add a basic datasheet for RI5CY	2015-09-09 18:35:07 +02:00
include	Remove movhi ALU opcode, it is of no use for RI5CY	2015-09-14 15:53:17 +02:00
.gitignore	Added vim swap file	2015-07-24 15:26:32 +02:00
alu.sv	Run through linter and do some cleanup	2015-09-15 13:08:26 +02:00
compressed_decoder.sv	Cleanup compressed decoder	2015-09-23 14:12:34 +02:00
controller.sv	This fixes the instruction fetch miss performance counter	2015-09-22 16:35:16 +02:00
cs_registers.sv	Fixed synopsis syntax error	2015-09-23 15:44:03 +02:00
debug_unit.sv	Rework pipeline flushes and exceptions	2015-08-31 10:02:55 +02:00
decoder.sv	Decentralize stall control	2015-09-21 18:26:08 +02:00
ex_stage.sv	Decentralize stall control	2015-09-21 18:26:08 +02:00
exc_controller.sv	Fix exception problem after stages are more independent	2015-09-24 13:16:18 +02:00
hwloop_controller.sv	Finish hwloops addition	2015-09-07 03:40:28 +02:00
hwloop_regs.sv	Cleanup unneeded signals and dead code	2015-09-02 18:07:44 +02:00
id_stage.sv	Prefetcher now tells the core when it is safe to shut down	2015-09-24 16:32:17 +02:00
if_stage.sv	Fix exception problem after stages are more independent	2015-09-24 13:16:18 +02:00
load_store_unit.sv	Decentralize stall control	2015-09-21 18:26:08 +02:00
mult.sv	Run through linter and do some cleanup	2015-09-15 13:08:26 +02:00
prefetch_buffer.sv	Rename instr_core_intf to prefetch_buffer, add if_busy signal again	2015-09-10 13:12:19 +02:00
prefetch_L0_buffer.sv	Prefetcher now tells the core when it is safe to shut down	2015-09-24 16:32:17 +02:00
register_file.sv	Fix linting errors/warnings and remove dead signals	2015-08-28 17:15:55 +02:00
riscv_core.sv	Fix exception problem after stages are more independent	2015-09-24 13:16:18 +02:00