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https://github.com/lowRISC/ibex.git
synced 2025-04-22 04:47:25 -04:00
This should fix most of the debug features
Basic test passes now, next step is to try and test it with an interactive gdb
This commit is contained in:
Andreas Traber
parent
6ba66dc141
commit
5da32ba5ec
4 changed files with 51 additions and 22 deletions
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@ -44,11 +44,11 @@ module riscv_debug_unit
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output logic [31:0] dbginf_data_o,
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// signals to core
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output logic dbg_st_en_o, // Single-step trace mode enabled
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output logic dbg_step_en_o, // Single-step trace mode enabled
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output logic [1:0] dbg_dsr_o, // debug stop register
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output logic stall_core_o,
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output logic flush_pipe_o,
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output logic stop_req_o,
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input logic trap_i,
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output logic sp_mux_o,
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@ -91,7 +91,7 @@ module riscv_debug_unit
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bp_fsm_ns = bp_fsm_cs;
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stall_core_o = 1'b0;
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dbginf_bp_o = 1'b0;
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flush_pipe_o = 1'b0;
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stop_req_o = 1'b0;
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case (bp_fsm_cs)
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Idle:
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@ -104,7 +104,7 @@ module riscv_debug_unit
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end
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else if(dbginf_stall_i)
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begin
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flush_pipe_o = 1'b1;
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stop_req_o = 1'b1;
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bp_fsm_ns = DebugStall;
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end
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end
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@ -112,7 +112,7 @@ module riscv_debug_unit
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// A stall from adv dbg unit was seen, flush the pipeline and wait for unstalling
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DebugStall:
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begin
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flush_pipe_o = 1'b1;
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stop_req_o = 1'b1;
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if(trap_i == 1'b1)
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begin
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@ -137,7 +137,7 @@ module riscv_debug_unit
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// data to GPRs and SPRs
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assign regfile_wdata_o = dbginf_data_i;
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assign dbg_st_en_o = dmr1_q[0];
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assign dbg_step_en_o = dmr1_q[0];
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assign dbg_dsr_o = dsr_q;
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assign npc_o = dbginf_data_i;
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@ -30,6 +30,8 @@ module riscv_exc_controller
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output logic req_o,
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input logic ack_i,
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output logic trap_hit_o,
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// to IF stage
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output logic [1:0] pc_mux_o, // selects target PC for exception
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output logic [4:0] vec_pc_mux_o, // selects interrupt handler for vectorized interrupts
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@ -39,6 +41,7 @@ module riscv_exc_controller
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input logic irq_enable_i, // interrupt enable bit from CSR
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// from decoder
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input logic trap_insn_i, // trap instruction encountered (EBREAK)
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input logic illegal_insn_i, // illegal instruction encountered
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input logic ecall_insn_i, // ecall instruction encountered
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input logic eret_insn_i, // eret instruction encountered
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@ -48,7 +51,12 @@ module riscv_exc_controller
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// to CSR
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output logic [5:0] cause_o,
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output logic save_cause_o
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output logic save_cause_o,
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// from debug unit
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input logic dbg_stop_req_i,
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input logic dbg_step_en_i,
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input logic [1:0] dbg_dsr_i
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);
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@ -61,11 +69,25 @@ module riscv_exc_controller
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integer i;
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assign req_int = illegal_insn_i
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| ecall_insn_i
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// a trap towards the debug unit is generated when one of the
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// following conditions are true:
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// - ebreak instruction encountered
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// - single-stepping mode enabled
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// - illegal instruction exception and IIE bit is set
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// - IRQ and INTE bit is set and no exception is currently running
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// - Debuger requests halt
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assign trap_hit_o = trap_insn_i
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| dbg_stop_req_i
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| dbg_step_en_i
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| (illegal_insn_i & dbg_dsr_i[`DSR_IIE])
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| (irq_enable_i & (|irq_i) & dbg_dsr_i[`DSR_INTE]);
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// request for exception/interrupt
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assign req_int = ecall_insn_i
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| lsu_load_err_i
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| lsu_store_err_i
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| (irq_enable_i & (|irq_i));
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| (illegal_insn_i & (~dbg_dsr_i[`DSR_IIE]))
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| (irq_enable_i & (|irq_i) & (~dbg_dsr_i[`DSR_INTE]));
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// Exception cause and ISR address selection
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@ -74,7 +96,7 @@ module riscv_exc_controller
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cause_int = 6'b0;
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pc_mux_int = 'x;
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if (irq_enable_i) begin
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if (irq_enable_i & (~dbg_dsr_i[`DSR_INTE])) begin
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// pc_mux_int is a critical signal, so try to get it as soon as possible
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if (|irq_i)
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pc_mux_int = `EXC_PC_IRQ;
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@ -93,7 +115,7 @@ module riscv_exc_controller
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pc_mux_int = `EXC_PC_ECALL;
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end
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if (illegal_insn_i) begin
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if (illegal_insn_i & (~dbg_dsr_i[`DSR_IIE])) begin
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cause_int = 6'b0_00010;
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pc_mux_int = `EXC_PC_ILLINSN;
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end
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15
id_stage.sv
15
id_stage.sv
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@ -141,8 +141,8 @@ module riscv_id_stage
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input logic lsu_store_err_i,
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// Debug Unit Signals
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input logic dbg_flush_pipe_i,
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input logic dbg_st_en_i,
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input logic dbg_stop_req_i,
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input logic dbg_step_en_i,
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input logic [1:0] dbg_dsr_i,
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input logic dbg_stall_i,
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output logic dbg_trap_o,
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@ -213,7 +213,6 @@ module riscv_id_stage
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logic exc_req, exc_ack; // handshake
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logic trap_hit;
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assign trap_hit = 1'b0; // TODO: Fix
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// Register file interface
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logic [4:0] regfile_addr_ra_id;
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@ -734,6 +733,8 @@ module riscv_id_stage
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.req_o ( exc_req ),
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.ack_i ( exc_ack ),
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.trap_hit_o ( trap_hit ),
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// to IF stage
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.pc_mux_o ( exc_pc_mux_o ),
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.vec_pc_mux_o ( exc_vec_pc_mux_o ),
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@ -742,6 +743,7 @@ module riscv_id_stage
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.irq_i ( irq_i ),
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.irq_enable_i ( irq_enable_i ),
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.trap_insn_i ( is_decoding_o & trap_insn ),
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.illegal_insn_i ( is_decoding_o & illegal_insn_dec ),
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.ecall_insn_i ( is_decoding_o & ecall_insn_dec ),
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.eret_insn_i ( is_decoding_o & eret_insn_dec ),
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@ -750,7 +752,12 @@ module riscv_id_stage
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.lsu_store_err_i ( lsu_store_err_i ),
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.cause_o ( exc_cause_o ),
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.save_cause_o ( save_exc_cause_o )
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.save_cause_o ( save_exc_cause_o ),
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// Debug Signals
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.dbg_stop_req_i ( dbg_stop_req_i ),
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.dbg_step_en_i ( dbg_step_en_i ),
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.dbg_dsr_i ( dbg_dsr_i )
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);
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@ -197,9 +197,9 @@ module riscv_core
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// Debug Unit
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logic dbg_stall;
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logic dbg_flush_pipe;
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logic dbg_stop_req;
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logic dbg_trap;
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logic dbg_st_en; // single-step trace mode enabled
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logic dbg_step_en; // single-step trace mode enabled
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logic [1:0] dbg_dsr; // Debug Stop Register
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logic dbg_reg_mux;
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@ -400,8 +400,8 @@ module riscv_core
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.lsu_store_err_i ( lsu_store_err ),
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// Debug Unit Signals
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.dbg_flush_pipe_i ( dbg_flush_pipe ),
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.dbg_st_en_i ( dbg_st_en ),
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.dbg_stop_req_i ( dbg_stop_req ),
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.dbg_step_en_i ( dbg_step_en ),
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.dbg_dsr_i ( dbg_dsr ),
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.dbg_stall_i ( dbg_stall ),
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.dbg_trap_o ( dbg_trap ),
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@ -640,11 +640,11 @@ module riscv_core
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.dbginf_data_o ( dbginf_data_o ),
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// To/From Core
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.dbg_st_en_o ( dbg_st_en ),
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.dbg_step_en_o ( dbg_step_en ),
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.dbg_dsr_o ( dbg_dsr ),
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.stall_core_o ( dbg_stall ),
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.flush_pipe_o ( dbg_flush_pipe ),
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.stop_req_o ( dbg_stop_req ),
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.trap_i ( dbg_trap ),
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// register file access
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