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Updated all file headers
This commit is contained in:
Sven Stucki
parent
10bc98382e
commit
bb2fbf8e54
14 changed files with 35 additions and 57 deletions
5
alu.sv
5
alu.sv
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@ -9,9 +9,9 @@
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// //
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// //
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// Create Date: 19/09/2013 //
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// Design Name: Pipelined Processor //
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// Design Name: RISC-V processor core //
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// Module Name: alu.sv //
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// Project Name: Processor //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Arithmetic logic unit of the pipelined processor //
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@ -25,7 +25,6 @@
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// //
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// //
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// //
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// //
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////////////////////////////////////////////////////////////////////////////////
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`include "defines.sv"
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@ -7,9 +7,9 @@
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// //
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// //
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// Create Date: 10/06/2015 //
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// Design Name: Compressed Instruction Decoder //
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// Module Name: id_stage.sv //
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// Project Name: RiscV //
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// Design Name: Compressed instruction decoder //
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// Module Name: compressed_decoder.sv //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Decodes RISC-V compressed instructions into their RV32 //
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@ -6,16 +6,16 @@
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// Additional contributions by: //
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// Igor Loi - igor.loi@unibo.it //
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// Andreas Traber - atraber@student.ethz.ch //
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// //
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// Sven Stucki - svstucki@student.ethz.ch //
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// //
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// //
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// Create Date: 19/09/2013 //
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// Design Name: Pipelined OpenRISC Processor //
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// Design Name: RISC-V processor core //
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// Module Name: controller.sv //
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// Project Name: OR10N //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: CPU Controller of the pipelined processor //
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// Description: Main CPU controller of the processor //
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// //
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// //
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// Revision: //
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@ -7,9 +7,9 @@
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// //
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// //
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// Create Date: 25/05/2015 //
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// Design Name: Pipelined Processor //
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// Design Name: RISC-V processor core //
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// Module Name: cs_registers.sv //
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// Project Name: Processor //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Control and Status Registers (CSRs) loosely following the //
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14
ex_stage.sv
14
ex_stage.sv
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@ -6,22 +6,18 @@
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// //
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// Additional contributions by: //
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// Igor Loi - igor.loi@unibo.it //
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// Sven Stucki - svstucki@student.ethz.ch //
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// //
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// //
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// Create Date: 01/07/2014 //
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// Design Name: Execute stage //
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// Design Name: Excecute stage //
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// Module Name: ex_stage.sv //
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// Project Name: OR10N //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Execution stage: Host Alu and Multiplier //
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// Description: Execution stage: Hosts ALU and MAC unit //
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// ALU: computes additions/subtractions/comparisons //
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// (in a pure combinational way) //
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// Multiplier: //
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// 32bit multiplication: takes two cycles to complete. The //
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// Result goes to the register file (only the 32 lsb) //
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// 64bit multiplication(l.muld): takes two cycles to complete //
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// Result goes to sp register maclo(32lsb) and machi(32msb) //
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// MAC: //
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// //
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// //
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// Revision: //
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@ -6,11 +6,10 @@
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// Additional contributions by: //
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// //
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// //
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// //
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// Create Date: 20/01/2015 //
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// Design Name: Pipelined OpenRISC Processor //
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// Design Name: RISC-V processor core //
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// Module Name: exc_controller.sv //
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// Project Name: OR10N //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Exception Controller of the pipelined processor //
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@ -13,7 +13,7 @@
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// Create Date: 19/09/2013 //
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// Design Name: Decode stage //
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// Module Name: id_stage.sv //
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// Project Name: RiscV //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Decode stage of the core. It decodes the instructions //
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@ -28,7 +28,6 @@
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// //
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// //
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// //
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// //
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////////////////////////////////////////////////////////////////////////////////
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@ -11,9 +11,9 @@
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// //
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// //
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// Create Date: 01/07/2014 //
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// Design Name: Instruction fetch stage //
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// Design Name: RISC-V processor core //
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// Module Name: if_stage.sv //
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// Project Name: RiscV //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Instruction fetch unit: Selection of the next PC, and //
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@ -42,8 +42,8 @@ module if_stage
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// Output of IF Pipeline stage
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output logic [31:0] instr_rdata_id_o, // read instruction is sampled and sent to ID stage for decoding
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output logic [31:0] current_pc_if_o, // "current" pc program counter
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output logic [31:0] current_pc_id_o, // current pc program counter
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output logic [31:0] current_pc_if_o, // program counter of IF stage
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output logic [31:0] current_pc_id_o, // program counter of ID stage
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// From to Instr memory
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input logic [31:0] instr_rdata_i, // Instruction read from instruction memory /cache
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@ -8,9 +8,9 @@
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// //
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// //
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// Create Date: 06/08/2014 //
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// Design Name: Instruction Fetch interface //
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// Design Name: RISC-V processor core //
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// Module Name: instr_core_interface.sv //
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// Project Name: OR10N //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Instruction Fetch interface used to properly handle //
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@ -21,8 +21,6 @@
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// //
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// //
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// //
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// //
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// //
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////////////////////////////////////////////////////////////////////////////////
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@ -10,7 +10,7 @@
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// Create Date: 01/07/2014 //
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// Design Name: Load Store Unit //
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// Module Name: load_store_unit.sv //
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// Project Name: OR10N //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Load Store Unit, used to eliminate multiple access during //
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@ -89,7 +89,7 @@ module load_store_unit
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///////////////////////////////// BE generation ////////////////////////////////
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always_comb
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begin
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casex (data_type_ex_i) // Data type 00 Word, 01 Half word, 11,10 byte
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case (data_type_ex_i) // Data type 00 Word, 01 Half word, 11,10 byte
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2'b00:
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begin // Writing a word
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if (misaligned_st == 1'b0)
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@ -129,7 +129,8 @@ module load_store_unit
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end
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end
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2'b1X: begin // Writing a byte
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2'b10,
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2'b11: begin // Writing a byte
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case (data_addr_ex_i[1:0])
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2'b00: data_be = 4'b0001;
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2'b01: data_be = 4'b0010;
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@ -137,7 +138,7 @@ module load_store_unit
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2'b11: data_be = 4'b1000;
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endcase; // case (data_addr_ex_i[1:0])
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end
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endcase; // casex (data_type_ex_i)
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endcase; // case (data_type_ex_i)
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end
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// prepare data to be written to the memory
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12
mult.sv
12
mult.sv
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@ -8,17 +8,13 @@
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// //
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// //
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// Create Date: 19/09/2013 //
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// Design Name: Pipelined Processor //
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// Design Name: Vectorial Multiplier and MAC //
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// Module Name: mult.sv //
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// Project Name: Processor //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Multiplier of the pipelined processor //
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// Design ware multiplier requires two cycles to complete. //
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// Generic multiplier requires only one cycle. result will be //
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// stored in a FF. Best synthesis results are achieved with //
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// moving the result register in the multiplier with automatic//
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// retiming! //
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// Description: Advanced MAC unit for PULP. //
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// //
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// //
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// Revision: //
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// Revision v0.1 - File Created //
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@ -33,13 +33,6 @@ module riscv_register_file
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localparam NUM_WORDS = 2**ADDR_WIDTH;
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// Read address register, located at the input of the address decoder
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logic [ADDR_WIDTH-1:0] RAddrRegxDPa;
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logic [ADDR_WIDTH-1:0] RAddrRegxDPb;
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logic [ADDR_WIDTH-1:0] RAddrRegxDPc;
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logic [NUM_WORDS-1:0] RAddrOneHotxD;
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logic [ADDR_WIDTH-1:0] s_raddr_c;
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logic [DATA_WIDTH-1:0] MemContentxDP[NUM_WORDS];
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logic [NUM_WORDS-1:0] WAddrOneHotxDa;
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@ -57,8 +50,6 @@ module riscv_register_file
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int unsigned i;
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int unsigned j;
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int unsigned k;
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int unsigned l;
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int unsigned m;
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genvar x;
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genvar y;
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@ -797,7 +797,6 @@ module riscv_core
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// Execution trace generation
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// synopsys translate_off
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/* verilator lint off */
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`ifdef TRACE_EXECUTION
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integer f;
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string fn;
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// Create Date: 01/07/2014 //
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// Design Name: Write Back stage //
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// Module Name: wb_stage.sv //
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// Project Name: OR10N //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Execution stage: hosts a Multiplexer that select data to //
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