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Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
38 commits 21 branches 8 tags 70 MiB
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Sven Stucki bb2fbf8e54 Updated all file headers
2015-07-24 15:26:12 +02:00
include Fixed Verilator width warnings where appropriate 2015-07-23 01:59:45 +02:00
alu.sv Updated all file headers 2015-07-24 15:26:12 +02:00
compressed_decoder.sv Updated all file headers 2015-07-24 15:26:12 +02:00
controller.sv Updated all file headers 2015-07-24 15:26:12 +02:00
cs_registers.sv Updated all file headers 2015-07-24 15:26:12 +02:00
debug_unit.sv Initial RiscV core commit; still in an early stage, but ALU instructions work 2015-04-01 11:11:07 +02:00
ex_stage.sv Updated all file headers 2015-07-24 15:26:12 +02:00
exc_controller.sv Updated all file headers 2015-07-24 15:26:12 +02:00
id_stage.sv Updated all file headers 2015-07-24 15:26:12 +02:00
if_stage.sv Updated all file headers 2015-07-24 15:26:12 +02:00
instr_core_interface.sv Updated all file headers 2015-07-24 15:26:12 +02:00
load_store_unit.sv Updated all file headers 2015-07-24 15:26:12 +02:00
mult.sv Updated all file headers 2015-07-24 15:26:12 +02:00
register_file.sv Updated all file headers 2015-07-24 15:26:12 +02:00
riscv_core.sv Updated all file headers 2015-07-24 15:26:12 +02:00
wb_stage.sv Updated all file headers 2015-07-24 15:26:12 +02:00