Commit graph

171 commits

Author SHA1 Message Date
Pirmin Vogel
a2184f9ec7 Align ALU comparison op naming to instruction names
By default, ops are signed in RISC-V. As opposed to the U suffix for
designating an op as being unsigned, there is no suffix for designating
ops as being signed.
2019-05-07 13:30:07 +01:00
Pirmin Vogel
8e5219fac3 Remove unused parameters related to PULP custom ISA extensions 2019-05-07 13:30:07 +01:00
Philipp Wagner
f9ad280d0c Cleanup includes and defines
- Move ibex_tracer_defines.sv and ibex_defines.sv out of the 'include'
  directory, since these files are not actually included.
- Remove ibex_config.sv, it's mostly unused code. The remaining defines,
  SYNTHESIS, ASIC_SYNTHESIS, TRACE_EXECUTION, and CHECK_MISALIGNED should
  be set through command-line flags to the simulation/synthesis tools.

Initial version by Nils Gräf.
2019-05-03 17:30:29 +01:00
Alex Bradbury
7e81f6f4eb Standardise "subheadings" in code comments
The code base made extensive use of ASCII art headings/subheadings in
comments to delineate code. Switch to a more space efficient and easier
to edit format:

/////////
// Foo //
/////////
2019-04-26 15:09:00 +01:00
Nils Graf
af77da9673 Fix lint issues in ibex_tracer 2019-04-26 15:09:00 +01:00
Philipp Wagner
bae56557e9 Prevent sleep mode on debug request
Debug requests are essentially interrupts and we need to prevent sleep
(or wake up the core) if we get a debug request.
2019-04-26 15:09:00 +01:00
Philipp Wagner
672929a9b7 Remove clock_en_i port from toplevel
The clock_en_i signal is unused within the module, as the clock_en
signal is generated from internal core state.
2019-04-26 15:09:00 +01:00
Philipp Wagner
48c0b34b38 Various fixes to debug implementation
This commit updates the RISC-V debug spec-compliant debug implementation
by incorporating changes mostly done by Robert Balas on the RI5CY core.

Most notably, single stepping works after this patch is applied.

With this patch the RISC-V debug compliance test built into OpenOCD
passes fully.
2019-04-26 15:09:00 +01:00
Philipp Wagner
4d0d59db8e Include executed instruction in dbg message
If an illegal instruction is executed we display a message in
simulation. This message now also contains the instruction itself, not
only the program counter.
2019-04-26 15:09:00 +01:00
Philipp Wagner
0b8b6b6d96 Comment on outdated trap handler impl.
Ibex currently implements a non-standard vectored trap handler which was
allowed according to a pre-1.10 Privileged Spec, but doesn't comply to
the current spec any more. Changes are required to both software (crt)
and hardware implementation. Until that happens at least explain what's
going on for people reading the current spec.
2019-04-26 15:09:00 +01:00
Philipp Wagner
cec232b36d Set dcsr.priv to M-mode on reset
Port of RI5CY commit 7f4a446f95f02f5ce517c0abe32b4095eb10c0de
2019-04-26 15:09:00 +01:00
Philipp Wagner
c8c1831117 Use struct and named constants for DCSR
Code cleanup only, no functional change.

Port of RI5CY commit 2a1de5977321080e02140609fb6b50c689129d81
2019-04-26 15:09:00 +01:00
Philipp Wagner
401e7e1e3c Switch to execution-based debug
This commit switches the ibex core from a custom debug system to an
execution-based, standard RISC-V debug system. The port is based on a
port done for the RI5CY core.
2019-04-26 15:09:00 +01:00
Philipp Wagner
ce312d0232 Support misa CSR
The misa CSR gives information about the implemented ISA.
2019-04-26 15:09:00 +01:00
Philipp Wagner
c4c4b8f1e4 Make RV32E/RV32M parameters bits
These parameters are boolean, use the "bit" data type to ensure their
value range.
2019-04-26 15:09:00 +01:00
Philipp Wagner
923fb624b0 Support fence as nop
Previously, the "fence" instruction was throwing an illegal instruction
exception. Now fence is handled as "nop", i.e. effectively ignored.

Ignoring fence is OK in the current system setup with no caches, and
will need to be reconsidered once caches are added.
2019-04-26 15:09:00 +01:00
Philipp Wagner
ef8acb38a9 Add source file list (*.f file) 2019-04-26 15:09:00 +01:00
Scott Johnson
6b0475744d Code cleanup
Fix errors and warnings reported by lint tools, and clean up the code
according to our coding style. Move all imports into the module.
2019-04-26 15:09:00 +01:00
Philipp Wagner
8813f57624 Add Doxygen-style module descriptions
We leave the existing longer headers in place for author information.
2019-04-26 15:08:30 +01:00
Alex Bradbury
27e68bd76e Convert from Solderpad to standard Apache 2.0 license
This change has been informed by advice from the lowRISC legal
committee.

The Solderpad 0.51 license states "the Licensor permits any Work
licensed under this License, at the option of the Licensee, to be
treated as licensed under the Apache License Version 2.0". We use this
freedom to convert license markings to Apache 2.0. This commit ensures
that we retain all authorship and copyright attribution information.
2019-04-26 15:05:17 +01:00
Philipp Wagner
e9e5a719bc Move RTL code into rtl/ directory
This gives us a bit of space in the source tree for documentation,
verification, utilities, and much more.
2019-04-26 15:05:17 +01:00