This commit clarifies why CSR-related pipeline flushes are needed
(e.g. when enabling interrupts), only introduces them when doing the
critical modifications (write/set bits in `mstatus` and `mie` CSRs
for enabling interrupts, reads and clears are uncritical for these
CSRs), and makes sure the controller is actually able to start
handling interrupts while doing a CSR-related pipeline flush.
This resolveslowrisc/ibex#6.
- Add required signals to top-level
- Propagate error through fetch stages
- Add new exception type
- Update documentation for new exception type
- Resolves issue #109
This commit makes the BASE field of the `mtvec` CSR writable to
allow changing the trap-vector base address at runtime without
changing the boot address input. Similar to the boot address,
the trap-vector base address must always be aligned to 256 bytes.
At bootup, the trap-vector base address is initialized to the boot
address.
This commit resolveslowrisc/ibex#118.
Most of this work has been done by @ivanmgribeiro as part of
lowrisc/ibex#193.
* ID stage: make single-cycle instr clear `instr_multicycle_done_q`
Previously, this signal was only cleared when starting the next
multi-cycle instruction.
* ID stage: only eval `instr_multicycle_done_q` for multi-cycle instr
This signal should only be evaluated if the ID/EX stage currently
executes a multi-cycle instruction. Without this commit, the signal
is also evaluated for single-cycle instructions and can for example
cause the register file write enable to not be de-asserted in case of
stalls in the IF stage.
This bug was repored by @udinator. This resolveslowrisc/ibex#216.
To enable recoverable non-maskeable interrupts (NMIs), an additional
set of registers is needed to backup `mstatus.MPP/MPIE` as well as
`mepc` and `mcause`. This is currently not part of the RISC-V Priv
Spec (v1.11). This commit adds these registers called `mstack` CSRs
according to the following proposal:
https://github.com/riscv/riscv-isa-manual/issues/261
These CSRs are only accessed by the hardware and not accessible to
software running on the core.
This commit adds 15 local fast interrupt lines managed through
the `mie` and `mip` CSRs directly, and removes the old legacy
interrupts including the internal controller.
This commit adds the `mip` and `mie` CSRs as well as the software,
timer and external interrupts.
Currently these interrupts are overlapped with some of the legacy
interrupts, i.e., the core will jump to the same address for different
interrupts. For example, the software interrupt has the same ID as
legacy interrupt #3. Thus, the handler must read the `mip` register
to find out whether the interrupt routine has been entered because of
the software interrupt or the legacy interrupt.
Eventually, the number of legacy interrupts will be reduced to avoid
this overlapping, and they will be connected to the `mie` and `mip`
CSRs directly.
We want people to get an error when compiling the tracer with Verilator:
this file should not be used with Verilator. An error is better than
silently getting the wrong result.
This change is slighly painful, but a necessary cleanup around the
tracer.
- We now provide a separate core file for the tracer, called
"ibex_tracer.core" (in line with "ibex_tracer.sv"). The core is called
"lowrisc:ibex:ibex_tracer".
- The toplevel wrapper with tracing enabled got renamed to
"ibex_core_tracing.sv", and the core file is correspondingly called
"ibex_core_tracing.core. The core in it is called
"lowrisc:ibex:ibex_core_tracing".
- Finally to keep symmetry, the toplevel of Ibex itself got renamed in
the core file from "lowrisc:ibex:ibex" to "lowrisc:ibex:ibex_core".
This ensures that we have the same name for the core file, the source
entry point, and the core name.
IMPORTANT NOTE:
If you apply this change and use fusesoc, you need to adjust the name of
the core dependency from "lowrisc:ibex:ibex" to
"lowrisc:ibex:ibex_core".
This file doesn't contain defines any more, but a normal SV package.
The diff is best viewed without whitespace changes, as the reindents
cause a lof of diff noise.
Fixeslowrisc/ibex#173
The ibex_tracer_define.sv file was removed from the FuseSoC core files,
but not from the src_files.yml (for Bender) and the .f file.
This is in line with the changes made in
f12b94c2a2.
The custom reg-reg load instruction was added in the original design but
is no longer needed. This commit removes it. Also, load instructions
with `instr[14:12] == 3'b110` are now decoded as illegal.
This resolves#25.
Without this commit, the PC is still set to a possible wrong jump
target on illegal JALR instructions ultimately causing the wrong PC
being saved to `mepc` during the illegal instruction exception.
This bug has been reported by @taoliug. This commit resolves#170.
This commit fixes the write back FSM to not store values returned from
memory to the register file when the LSU is reporting a load error.
This bug was reported by @ivanmgribeiro. This commit resolves#162.
This commit changes the controller to save the PC of the next
instruction to the dpc CSR when entering debug mode upon a halt
request instead of the PC of the current instruction (only valid
for EBREAK instructions).
This bug was reported by @taoliug. This resolves#164.
This commit fixes two bugs in the decoder:
1. For illegal branch condition selections, the illegal instruction
condition must be signaled as long as the instruction is being executed
and not just during the first cycle, as the controller cannot interrupt
multicycle instructions.
2. Illegal instructions should also be signaled when `instr[28]` is set
for register-register ALU operations. Previously, these were not
signaled as the original design used `instr[28]` to encode custom bit-
manipulation instructions.
These bugs were discovered by @taoliug. This resolves issue #163.
The RVFI implementation make use of signals from the decoder and
controller to detect the state of the processor.
Especially the signal for a new and retired instruction.
* Controller: remove impossible condition for `DBG_TAKEN_IF`
There is no way to jump into `DBG_TAKEN_IF` because of an EBREAK
instruction. Thus, this case also does not need to be checked.
* Controller: do not enter debug when `debug_req_i` goes low
With this commit, the core is prevented from entering debug mode when
the debug request signal is deasserted during that procedure.
Previously, the core would still enter debug mode but not updating the
debug CSR.
This resolves#153 reported by @taoliug.
* Update ibex_controller.sv
The FSM now uses input signals for interrupt and debug request handling
that depend on whether the core is in debug mode. This avoids the need
for many `debug_mode_q` guards and somewhat simplifies the FSM.
If in debug mode, the core shall not handle interrupts according to the
spec anyway.
This commit moves the generation of these signals into the ID stage
to generate it with more accurate timing. More precisely, an
instruction is now considered as retired once it has been completely
executed and not once the next instruction is pushed into the IF-ID
pipeline register.
Also, it no longer depends on whether the instruction was valid or
illegal. For RVFI and the tracer, also illegal instructions must be
considered.
Previsouly, the regfile write enable output of the decoder was always
fed through the WB FSM which is unnecessary except for stores and
mult/div operations.
Once the core is executing, the IF stage now only gets two signals
from the controller: One to clear the instruction valid output and one
to prevent the IF stage from pushing new instructions.
The former `if_valid_o` of the IF stage has been renamed to clarify
that this is not a valid bit but just the write enable for the
pipeline register.
The register file shall not be written upon illegal CSR operations
and when the core is idle (waiting for new instructions). Otherwise
the write enable signal from the WB FSM/decoder is used.
Single stepping should execute exactly one more instruction, not abort
any running (multicycle) instructions, and only enter debug mode after
the current instruction is finished. In case the current instruction
leads to an exception, the exception registers must be set accordingly,
but the core must jump into debug mode instead of the exception
handler.
Previous to this commit, single stepping would immediately jump into
debug mode and ignore any exceptions.
This commit makes sure that interrupts and debug requests do not
interrupt currently running multicycle instructions. Priority is
given 1) to the currently running instruction, possible exceptions
caused by this instruction, 2) debug requests, 3) interrupt
requests.
Previously, currently running instructions were aborted upon
incoming debug and interrupt requests, which could corrupt the
processor state and lead to exceptions being ignored.
This commit resolves#108 and #121.
