prim_assert.sv is a file containing assertion macros (defines).
Previously, prim_assert.sv was compiled as normal SystemVerilog file.
This made the defines available for the whole compilation unit as soon
as they were defined. Since all cores using prim_assert depended (in
fusesoc) on the lowrisc:prim:assert core, prim_assert was always
compiled first, and the defines were visible in subsequent files.
All of that is only true if all files end up in one comilation unit. The
SV standard states that what makes up a compilation unit is
tool-defined, but also states that typically, passing multiple files (or
a file list/.f file) to a single tool invocation means that all files
end up in one compilation unit; if the tool is called multiple times,
then the files end up in separate compilation units.
Edalize (the fusesoc backend) doesn't guarantee either behavior, and so
it happens that for Vivado, Verilator, Cadence and Synopsys simulators,
all files are compiled into a single compilation unit. But for Riviera,
each file is a separate compilation unit.
To avoid relying on the definition of compilation units, and to do the
generally right thing (TM), this commit changes the code to always
include the prim_assert.sv file when it is used in a source file.
Include guards are introduced in the prim_assert.sv file to avoid
defining things twice.
This commit ensures that the assertions in the compressed decoder do
not fire if the compressed decoder sees invalid data from the prefetch
buffer.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit modifies the compressed decoder to forward the incoming
instruction to the output. It is marked as legal, unless:
1) the decoder cannot determine if the instruction is compressed (e.g.
because of unknown selector bits), or
2) the instruction is compressed but
a) it cannot be successfully decompressed (e.g. because of unknown
selector bits), or
b) it is indeed illegal.
In the case of 2b) the compressed decoder may output an illegal
decompressed instruction instead of the incoming instruction.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit replaces all X assignments in the RTL with defined
values. In addition, SystemVerilog Assertions are added to catch
invalid signal values in simulation. A new file containing the
corresponding assertion macros is added as well.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
We currently have a documentation block at the beginning of each file,
containing author credits and module-level documentation. The
module-level documentation is retained for historic reasons and
duplicated with the newer comments below it.
For the authors, maintaining author credits in the file is error-prone,
as this information gets outdated very soon. A more reliable way to see
who modified a file is to use the history information in git.
Additionally, we now have the CREDITS.md file, which lists all
contributors, even the ones which don't appear in the git history (e.g.
because the code was copied and commited by someone else).
This file doesn't contain defines any more, but a normal SV package.
The diff is best viewed without whitespace changes, as the reindents
cause a lof of diff noise.
Fixeslowrisc/ibex#173
It is not necessary to do this check in the compressed decoder. If a
compressed instruction in RV32E tries to access any register x16 - x31,
the regular decoder triggers an illegal instruction exception and the
controller writes the actual faulting (compressed) instruction to
`mtval`.
- Decoding must give precedence to rs2 (i.e. instr_i[6:2]) to
switch between C.MV and C.JR.
"C.MV is only valid when rs2̸=x0; the code points with rs2=x0
correspond to the C.JR instruction. The code points with rs2̸=x0
and rd=x0 are HINTs."
- C.JR is only valid with rs1==x0. Throw an illegal instruction
exception if that's not the case.
"C.JR is only valid when rs1̸=x0; the code point with rs1=x0
is reserved." RV32 Spec, p103
All spec references based on RISC-V Unprivileged ISA
V20190305-Base-Ratification
The RV32C Specification, p106 (RISC-V Unprivileged ISA
V20190305-Base-Ratification) states:
C.ADD adds the values in registers rd and rs2 and writes the result to
register rd. C.ADD expands into add rd, rd, rs2. C.ADD is only valid
when rs2̸=x0; the code points with rs2=x0 correspond to the C.JALR and
C.EBREAK instructions. The code points with rs2̸=x0 and rd=x0 are HINTs.
This essentially says: rs2 == x0 takes precedence when decoding, that's
instr[6:2]. The current code was written with the assumption of
instr[11:7] taking precedence, thus incorrectly decoding a C.ADD HINT.
Fixeslowrisc/ibex#64
This commit adds a `default` to all `unique case` statements. Also, in case
FSMs reach an undefined state, the `'X` is propagated to ease detection
in simulation. Both these changes are required by our coding guidelines.
The code base made extensive use of ASCII art headings/subheadings in
comments to delineate code. Switch to a more space efficient and easier
to edit format:
/////////
// Foo //
/////////
This change has been informed by advice from the lowRISC legal
committee.
The Solderpad 0.51 license states "the Licensor permits any Work
licensed under this License, at the option of the Licensee, to be
treated as licensed under the Apache License Version 2.0". We use this
freedom to convert license markings to Apache 2.0. This commit ensures
that we retain all authorship and copyright attribution information.
