The core ignores the lowest byte of the boot address and thus does not
support booting from addresses not aligned to 256 bytes. This commit
updates both the documentation accordingly and adds an assert to the
IF stage.
This commit replaces fully-specified, binary case statements with default
case by a simple one-line assignment to avoid linting errors. Removing the
default would also work but is more error prone if at a later point more
case are added and the statement is no longer fully-specified.
In case of interrupts, `exc_cause` carries the interrupt ID in the lower
bits and its MSB is 0 anyway. There is no need to forward only the lower
bits to the IF stage.
By default, ops are signed in RISC-V. As opposed to the U suffix for
designating an op as being unsigned, there is no suffix for designating
ops as being signed.
- Move ibex_tracer_defines.sv and ibex_defines.sv out of the 'include'
directory, since these files are not actually included.
- Remove ibex_config.sv, it's mostly unused code. The remaining defines,
SYNTHESIS, ASIC_SYNTHESIS, TRACE_EXECUTION, and CHECK_MISALIGNED should
be set through command-line flags to the simulation/synthesis tools.
Initial version by Nils Gräf.
The code base made extensive use of ASCII art headings/subheadings in
comments to delineate code. Switch to a more space efficient and easier
to edit format:
/////////
// Foo //
/////////
This commit updates the RISC-V debug spec-compliant debug implementation
by incorporating changes mostly done by Robert Balas on the RI5CY core.
Most notably, single stepping works after this patch is applied.
With this patch the RISC-V debug compliance test built into OpenOCD
passes fully.
If an illegal instruction is executed we display a message in
simulation. This message now also contains the instruction itself, not
only the program counter.
Ibex currently implements a non-standard vectored trap handler which was
allowed according to a pre-1.10 Privileged Spec, but doesn't comply to
the current spec any more. Changes are required to both software (crt)
and hardware implementation. Until that happens at least explain what's
going on for people reading the current spec.
This commit switches the ibex core from a custom debug system to an
execution-based, standard RISC-V debug system. The port is based on a
port done for the RI5CY core.
Previously, the "fence" instruction was throwing an illegal instruction
exception. Now fence is handled as "nop", i.e. effectively ignored.
Ignoring fence is OK in the current system setup with no caches, and
will need to be reconsidered once caches are added.
This change has been informed by advice from the lowRISC legal
committee.
The Solderpad 0.51 license states "the Licensor permits any Work
licensed under this License, at the option of the Licensee, to be
treated as licensed under the Apache License Version 2.0". We use this
freedom to convert license markings to Apache 2.0. This commit ensures
that we retain all authorship and copyright attribution information.
