This adds the configuration instantiated in Opentitan and adds
missing prim support to allow the TB to run that configuration.
Resolves#1362
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Follow OpenTitan's lead and move to Ubuntu 18.04 for the CI runner.
Ubuntu 16.04 comes with Python 3.5, which is EOL and causes more and
more issues.
Specificially, this update is triggered by rst2pdf not being installable
with pip's new dependency resolver (see also
https://github.com/rst2pdf/rst2pdf/issues/489#issuecomment-736652808).
Private CI has a separate list of ibex configurations it runs (there's
no sane way around that). Add a note to the pipeline configuration to
hopefully remember to keep them in sync, if that's desired (they don't
*have to* be in sync).
We now have an Ibex configuration
experimental-maxperf-pmp-bmfull-icache, which also enables the
instruction cache. Enable this configuration in public CI, which makes
it run the lint and RISC-V compliance jobs.
Put all build dependencies into a CI-specific script
(ci/install-build-deps.sh). No effort has been made to make this script
suitable for non-CI users.
Verible lint now supports waivers without regex and line arguments. Use
this new feature and remove the workaround we had in place.
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
Verible is still experimental, but having a newer version in CI helps us
to make use of some of its newer features as we move forward (such as
waivers).
This commit contains some final optimizations regarding the bit
manipulation extension as well as the parametrization into a balanced
version and a full performance version.
Balanced Version:
* Supports ZBB, ZBS, ZBF and ZBT extensions
* Dual cycle instructions:
ror[i], rol, cmov, cmix fsl, fsr[i]
* Everything else completes in a single cycle.
Full Version:
* Supports all 32b sub extensions.
* Dual cycle instructions:
ror[i], rol, cmov, cmix fsl, fsr[i], crc32[c], bext, bdep
* Everything else completes in a single cycle.
Notable Changes:
* bext/bdep are now multi-cycle: Sharing additional register
with multiplier module
* grev/gorc instructions are implemented in separate structures
rather than sharing the shifter or butterfly network.
* Speed up decision on using rs1 or rs3 for alu_operand_a by
introducing single-bit register, to identify ternary
instructions in their first cycle.
* Introduce enumerated parameter to chose bit manipulation
implementation
Signed-off-by: ganoam <gnoam@live.com>
Pyyaml is needed for primgen (coming next), and for ibex_config.py.
Install it through python-requirements.txt. This requires,
unfortunately, an uninstallation of the distribution-provided version
first (otherwise pip cannot install it).
Reduce CI times by using a packaged version of Verilator. The packaging
is done by me on Open Build Service, which provides Verilator packages
for various distributions. The packages are versioned to help choose the
exact version in CI.
This is experimental for now, let's see if that's a suitable path
forward in the longer term.
Note this doesn't introduce any testing of the RV32B instructions,
simply runs existing tests on a configuration with the RV32B extension
enabled.
Fixes#745
Use a toolchain in CI which has support for experimental bitmanip
patches. This toolchain is based on GCC 9.2.0 with additional bitmanip
patches, and reports itself as 10.0 experimental.
The toolchain was prepared by Luís Marques in
lowRISC/lowrisc-toolchains#11. Thanks!
Addresses part of #703
Run
```
fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:ibex:ibex_core
```
to format all source code with Verible's verilog_format tool.
This extends the core file to be able to call Verible for lint.
This requires an updated version of edalize with
https://github.com/olofk/edalize/issues/95 fixed. For the time being, we
use the same 'ot' branches of those tools as we do in OpenTitan. Once
Verible becomes officially supported we need to ensure that released
versions of fusesoc and edalize exist, and that this requirement is
properly documented.
Verilator will soon support the configuration file syntax of wildcard
matches for linter warnings to waive. Switch to the new syntax that
avoids line-based rule settings.
Recently changes in the RISC-V compliance repo have caused our tests to
fail. That indicent highlighted the issue that we use the latest master
version of the compliance suite without pinning the version.
This PR fixes that by pinning to a specific version where our tests
still succeeded.
Upstream PR to fix actual failure: https://github.com/riscv/riscv-compliance/pull/92
Works around #608
The Ubuntu xenial-provided versions of setuptools and pip don't parse
all metadata present in Python packages, especially not the "minimum
required Python version" bit. More and more packages are using this
information to limit Python 3.5-support to older versions of their
packages. In this case, the problem was caused by the "zipp" package,
which is a very remote dependency of fusesoc.
Fixes#597
Support initialization of memory by loading content from ELF files.
All segments of the ELF file with the type `PT_LOAD` are merged into a
temporary buffer and then forwarded to a predefined memory.
This is an addition for setting the memories with VMEM files.
Memories must implement `simutil_verilator_set_mem` to support the
setting of values with a width of 32 bits. A return value of 0 must
indicate a successful operation and 1 an error.
Memories are defined by a call to `RegisterMemoryArea()` before the
execution of the simulation, at which point the arguments are parsed and
the initialization is started. The memories are identified by unique
name. The design specific location is used to set the SystemVerilog
scope.
Registered memories can be printed by using `-l list`. The unique name
is used for `-l name,file.elf` together with the file path.
An optional part of the argument is the type of the file, `elf` or
`vmem`, and if not provided it is attempted to detect the type by
looking at the file extension.
The memory specific arguments which already existed accept now also ELF
files. They use predefined names and are included to keep the interface
stable.
Contents of an ELF segment which has a bigger memory size than file size
are not set. This is typically required for BSS sections for zero-ing
the memory.
simplesat (required by fusesoc) was broken by an update to the attrs
library. Now simplesat 0.8.2 has been released which fixes the issue, we
can remove the explicit pinning of the old attrs version.
This sets up Azure Pipelines to run the following two tasks:
- Run Verilator lint on the SystemVerilog code.
- Run the RISC-V compliance test suite for RV32IMC
