mirror of
https://github.com/lowRISC/ibex.git
synced 2025-04-20 11:57:12 -04:00
e1a7dcf37f
This commit clarifies why CSR-related pipeline flushes are needed (e.g. when enabling interrupts), only introduces them when doing the critical modifications (write/set bits in `mstatus` and `mie` CSRs for enabling interrupts, reads and clears are uncritical for these CSRs), and makes sure the controller is actually able to start handling interrupts while doing a CSR-related pipeline flush. This resolves lowrisc/ibex#6.
583 lines
21 KiB
Systemverilog
583 lines
21 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Copyright 2018 ETH Zurich and University of Bologna.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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////////////////////////////////////////////////////////////////////////////////
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// Engineer: Matthias Baer - baermatt@student.ethz.ch //
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// //
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// Additional contributions by: //
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// Igor Loi - igor.loi@unibo.it //
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// Andreas Traber - atraber@student.ethz.ch //
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// Sven Stucki - svstucki@student.ethz.ch //
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// Davide Schiavone - pschiavo@iis.ee.ethz.ch //
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// //
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// Design Name: Main controller //
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// Project Name: ibex //
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// Language: SystemVerilog //
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// //
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// Description: Main controller of the processor //
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// //
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////////////////////////////////////////////////////////////////////////////////
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/**
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* Main controller of the processor
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*/
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module ibex_controller (
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input logic clk_i,
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input logic rst_ni,
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input logic fetch_enable_i, // start decoding
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output logic ctrl_busy_o, // core is busy processing instrs
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output logic first_fetch_o, // core is at the FIRST FETCH stage
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// decoder related signals
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input logic illegal_insn_i, // decoder has an invalid instr
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input logic ecall_insn_i, // decoder has ECALL instr
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input logic mret_insn_i, // decoder has MRET instr
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input logic dret_insn_i, // decoder has DRET instr
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input logic wfi_insn_i, // decoder has WFI instr
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input logic ebrk_insn_i, // decoder has EBREAK instr
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input logic csr_pipe_flush_i, // do CSR-related pipeline flush
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// from IF-ID pipeline stage
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input logic instr_valid_i, // instr from IF-ID reg is valid
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input logic [31:0] instr_i, // instr from IF-ID reg, for mtval
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input logic [15:0] instr_compressed_i, // instr from IF-ID reg, for mtval
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input logic instr_is_compressed_i, // instr from IF-ID reg is compressed
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input logic instr_fetch_err_i, // instr from IF-ID reg has error
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input logic [31:0] pc_id_i, // instr from IF-ID reg address
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// to IF-ID pipeline stage
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output logic instr_valid_clear_o, // kill instr in IF-ID reg
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output logic id_in_ready_o, // ID stage is ready for new instr
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// to prefetcher
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output logic instr_req_o, // start fetching instructions
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output logic pc_set_o, // jump to address set by pc_mux
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output ibex_pkg::pc_sel_e pc_mux_o, // IF stage fetch address selector
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// (boot, normal, exception...)
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output ibex_pkg::exc_pc_sel_e exc_pc_mux_o, // IF stage selector for exception PC
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output ibex_pkg::exc_cause_e exc_cause_o, // for IF stage, CSRs
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// LSU
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input logic [31:0] lsu_addr_last_i, // for mtval
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input logic load_err_i,
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input logic store_err_i,
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// jump/branch signals
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input logic branch_set_i, // branch taken set signal
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input logic jump_set_i, // jump taken set signal
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// interrupt signals
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input logic csr_mstatus_mie_i, // M-mode interrupt enable bit
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input logic csr_msip_i, // software interrupt pending
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input logic csr_mtip_i, // timer interrupt pending
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input logic csr_meip_i, // external interrupt pending
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input logic [14:0] csr_mfip_i, // fast interrupt pending
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input logic irq_pending_i, // interrupt request pending
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input logic irq_nm_i, // non-maskeable interrupt
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// debug signals
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input logic debug_req_i,
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output ibex_pkg::dbg_cause_e debug_cause_o,
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output logic debug_csr_save_o,
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input logic debug_single_step_i,
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input logic debug_ebreakm_i,
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output logic csr_save_if_o,
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output logic csr_save_id_o,
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output logic csr_restore_mret_id_o,
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output logic csr_save_cause_o,
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output logic [31:0] csr_mtval_o,
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// stall signals
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input logic stall_lsu_i,
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input logic stall_multdiv_i,
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input logic stall_jump_i,
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input logic stall_branch_i,
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// performance monitors
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output logic perf_jump_o, // we are executing a jump
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// instruction (j, jr, jal, jalr)
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output logic perf_tbranch_o // we are executing a taken branch
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// instruction
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);
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import ibex_pkg::*;
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// FSM state encoding
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typedef enum logic [3:0] {
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RESET, BOOT_SET, WAIT_SLEEP, SLEEP, FIRST_FETCH, DECODE, FLUSH,
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IRQ_TAKEN, DBG_TAKEN_IF, DBG_TAKEN_ID
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} ctrl_fsm_e;
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ctrl_fsm_e ctrl_fsm_cs, ctrl_fsm_ns;
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logic nmi_mode_q, nmi_mode_d;
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logic debug_mode_q, debug_mode_d;
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logic load_err_q, load_err_d;
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logic store_err_q, store_err_d;
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logic stall;
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logic halt_if;
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logic halt_id;
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logic exc_req;
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logic exc_req_lsu;
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logic special_req;
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logic enter_debug_mode;
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logic handle_irq;
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logic [4:0] mfip_id;
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logic unused_csr_mtip;
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`ifndef SYNTHESIS
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// synopsys translate_off
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// make sure we are called later so that we do not generate messages for
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// glitches
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always_ff @(negedge clk_i) begin
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// print warning in case of decoding errors
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if ((ctrl_fsm_cs == DECODE) && instr_valid_i && illegal_insn_i) begin
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$display("%t: Illegal instruction (core %0d) at PC 0x%h: 0x%h", $time, ibex_core.core_id_i,
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ibex_id_stage.pc_id_i, ibex_id_stage.instr_rdata_i);
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end
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end
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// synopsys translate_on
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`endif
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////////////////
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// Exceptions //
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////////////////
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assign load_err_d = load_err_i;
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assign store_err_d = store_err_i;
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// exception requests
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assign exc_req = ecall_insn_i | ebrk_insn_i | illegal_insn_i | instr_fetch_err_i;
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// LSU exception requests
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assign exc_req_lsu = store_err_i | load_err_i;
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// special requests: special instructions, pipeline flushes, exceptions...
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assign special_req = mret_insn_i | dret_insn_i | wfi_insn_i | csr_pipe_flush_i |
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exc_req | exc_req_lsu;
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////////////////
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// Interrupts //
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////////////////
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assign enter_debug_mode = debug_req_i & ~debug_mode_q;
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// interrupts including NMI are ignored while in debug mode [Debug Spec v0.13.2, p.39]
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assign handle_irq = ~debug_mode_q &
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((irq_nm_i & ~nmi_mode_q) | (irq_pending_i & csr_mstatus_mie_i));
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// generate ID of fast interrupts, highest priority to highest ID
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always_comb begin : gen_mfip_id
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if (csr_mfip_i[14]) mfip_id = 5'd14;
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else if (csr_mfip_i[13]) mfip_id = 5'd13;
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else if (csr_mfip_i[12]) mfip_id = 5'd12;
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else if (csr_mfip_i[11]) mfip_id = 5'd11;
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else if (csr_mfip_i[10]) mfip_id = 5'd10;
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else if (csr_mfip_i[ 9]) mfip_id = 5'd9;
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else if (csr_mfip_i[ 8]) mfip_id = 5'd8;
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else if (csr_mfip_i[ 7]) mfip_id = 5'd7;
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else if (csr_mfip_i[ 6]) mfip_id = 5'd6;
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else if (csr_mfip_i[ 5]) mfip_id = 5'd5;
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else if (csr_mfip_i[ 5]) mfip_id = 5'd5;
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else if (csr_mfip_i[ 4]) mfip_id = 5'd4;
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else if (csr_mfip_i[ 3]) mfip_id = 5'd3;
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else if (csr_mfip_i[ 2]) mfip_id = 5'd2;
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else if (csr_mfip_i[ 1]) mfip_id = 5'd1;
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else mfip_id = 5'd0;
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end
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assign unused_csr_mtip = csr_mtip_i;
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/////////////////////
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// Core controller //
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/////////////////////
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always_comb begin
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// Default values
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instr_req_o = 1'b1;
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csr_save_if_o = 1'b0;
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csr_save_id_o = 1'b0;
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csr_restore_mret_id_o = 1'b0;
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csr_save_cause_o = 1'b0;
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csr_mtval_o = '0;
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pc_mux_o = PC_BOOT;
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pc_set_o = 1'b0;
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exc_pc_mux_o = EXC_PC_IRQ;
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exc_cause_o = EXC_CAUSE_INSN_ADDR_MISA; // = 6'h00
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ctrl_fsm_ns = ctrl_fsm_cs;
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ctrl_busy_o = 1'b1;
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first_fetch_o = 1'b0;
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halt_if = 1'b0;
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halt_id = 1'b0;
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debug_csr_save_o = 1'b0;
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debug_cause_o = DBG_CAUSE_EBREAK;
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debug_mode_d = debug_mode_q;
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nmi_mode_d = 1'b0;
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perf_tbranch_o = 1'b0;
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perf_jump_o = 1'b0;
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unique case (ctrl_fsm_cs)
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RESET: begin
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// just wait for fetch_enable
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instr_req_o = 1'b0;
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pc_mux_o = PC_BOOT;
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pc_set_o = 1'b1;
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if (fetch_enable_i) begin
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ctrl_fsm_ns = BOOT_SET;
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end
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end
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BOOT_SET: begin
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// copy boot address to instr fetch address
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instr_req_o = 1'b1;
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pc_mux_o = PC_BOOT;
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pc_set_o = 1'b1;
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ctrl_fsm_ns = FIRST_FETCH;
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end
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WAIT_SLEEP: begin
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ctrl_busy_o = 1'b0;
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instr_req_o = 1'b0;
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halt_if = 1'b1;
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halt_id = 1'b1;
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ctrl_fsm_ns = SLEEP;
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end
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SLEEP: begin
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// instruction in IF stage is already valid
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// we begin execution when an interrupt has arrived
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ctrl_busy_o = 1'b0;
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instr_req_o = 1'b0;
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halt_if = 1'b1;
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halt_id = 1'b1;
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// normal execution flow
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// in debug mode or single step mode we leave immediately (wfi=nop)
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if (irq_nm_i || irq_pending_i || debug_req_i || debug_mode_q || debug_single_step_i) begin
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ctrl_fsm_ns = FIRST_FETCH;
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end
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end
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FIRST_FETCH: begin
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first_fetch_o = 1'b1;
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// Stall because of IF miss
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if (id_in_ready_o) begin
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ctrl_fsm_ns = DECODE;
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end
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// handle interrupts
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if (handle_irq) begin
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// This assumes that the pipeline is always flushed before
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// going to sleep.
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ctrl_fsm_ns = IRQ_TAKEN;
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halt_if = 1'b1;
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halt_id = 1'b1;
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end
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// enter debug mode
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if (enter_debug_mode) begin
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ctrl_fsm_ns = DBG_TAKEN_IF;
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halt_if = 1'b1;
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halt_id = 1'b1;
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end
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end
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DECODE: begin
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// normal operating mode of the ID stage, in case of debug and interrupt requests,
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// priorities are as follows (lower number == higher priority)
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// 1. currently running (multicycle) instructions and exceptions caused by these
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// 2. debug requests
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// 3. interrupt requests
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if (instr_valid_i) begin
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// set PC in IF stage to branch or jump target
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if (branch_set_i || jump_set_i) begin
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pc_mux_o = PC_JUMP;
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pc_set_o = 1'b1;
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perf_tbranch_o = branch_set_i;
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perf_jump_o = jump_set_i;
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// get ready for special instructions, exceptions, pipeline flushes
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end else if (special_req) begin
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ctrl_fsm_ns = FLUSH;
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halt_if = 1'b1;
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halt_id = 1'b1;
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end
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// stall IF stage to not starve debug and interrupt requests, these just
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// need to wait until after the current (multicycle) instruction
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if ((enter_debug_mode || handle_irq) && stall) begin
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halt_if = 1'b1;
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end
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// single stepping:
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// execute a single instruction and then enter debug mode, in case of exceptions,
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// set registers but do not jump into handler [Debug Spec v0.13.2, p.44]
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if (debug_single_step_i && !debug_mode_q) begin
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halt_if = 1'b1;
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if (!special_req && !stall) begin
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ctrl_fsm_ns = DBG_TAKEN_IF;
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end
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end
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end // instr_valid_i
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if (!stall && !special_req) begin
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if (enter_debug_mode) begin
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// enter debug mode
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ctrl_fsm_ns = DBG_TAKEN_IF;
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halt_if = 1'b1;
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halt_id = 1'b1;
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end else if (handle_irq) begin
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// handle interrupt (not in debug mode)
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ctrl_fsm_ns = IRQ_TAKEN;
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halt_if = 1'b1;
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halt_id = 1'b1;
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end
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end
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end // DECODE
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IRQ_TAKEN: begin
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if (handle_irq) begin
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pc_mux_o = PC_EXC;
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pc_set_o = 1'b1;
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exc_pc_mux_o = EXC_PC_IRQ;
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csr_save_if_o = 1'b1;
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csr_save_cause_o = 1'b1;
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// interrupt priorities according to Privileged Spec v1.11 p.31
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if (irq_nm_i && !nmi_mode_q) begin
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exc_cause_o = EXC_CAUSE_IRQ_NM;
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nmi_mode_d = 1'b1; // enter NMI mode
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end else if (csr_mfip_i != 15'b0) begin
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exc_cause_o = exc_cause_e'({1'b1, mfip_id});
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end else if (csr_meip_i) begin
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exc_cause_o = EXC_CAUSE_IRQ_EXTERNAL_M;
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end else if (csr_msip_i) begin
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exc_cause_o = EXC_CAUSE_IRQ_SOFTWARE_M;
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end else begin // csr_mtip_i
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exc_cause_o = EXC_CAUSE_IRQ_TIMER_M;
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end
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end
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ctrl_fsm_ns = DECODE;
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end
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DBG_TAKEN_IF: begin
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// enter debug mode and save PC in IF to dpc
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// jump to debug exception handler in debug memory
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if (debug_single_step_i || debug_req_i) begin
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pc_mux_o = PC_EXC;
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pc_set_o = 1'b1;
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exc_pc_mux_o = EXC_PC_DBD;
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csr_save_if_o = 1'b1;
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debug_csr_save_o = 1'b1;
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csr_save_cause_o = 1'b1;
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if (debug_single_step_i) begin
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debug_cause_o = DBG_CAUSE_STEP;
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end else begin
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debug_cause_o = DBG_CAUSE_HALTREQ;
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end
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// enter debug mode
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debug_mode_d = 1'b1;
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end
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ctrl_fsm_ns = DECODE;
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end
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DBG_TAKEN_ID: begin
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// enter debug mode and save PC in ID to dpc, used when encountering
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// 1. EBREAK during debug mode
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// 2. EBREAK with forced entry into debug mode (ebreakm or ebreaku set).
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// regular ebreak's go through FLUSH.
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//
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// for 1. do not update dcsr and dpc, for 2. do so [Debug Spec v0.13.2, p.39]
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// jump to debug exception handler in debug memory
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if (ebrk_insn_i) begin
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pc_mux_o = PC_EXC;
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pc_set_o = 1'b1;
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exc_pc_mux_o = EXC_PC_DBD;
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// update dcsr and dpc
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if (debug_ebreakm_i && !debug_mode_q) begin // ebreak with forced entry
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// dpc (set to the address of the EBREAK, i.e. set to PC in ID stage)
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csr_save_cause_o = 1'b1;
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csr_save_id_o = 1'b1;
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// dcsr
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debug_csr_save_o = 1'b1;
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debug_cause_o = DBG_CAUSE_EBREAK;
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end
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// enter debug mode
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debug_mode_d = 1'b1;
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end
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ctrl_fsm_ns = DECODE;
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end
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FLUSH: begin
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// flush the pipeline
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halt_if = 1'b1;
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halt_id = 1'b1;
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ctrl_fsm_ns = DECODE;
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// exceptions: set exception PC, save PC and exception cause
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// exc_req_lsu is high for one clock cycle only (in DECODE)
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if (exc_req || store_err_q || load_err_q) begin
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pc_set_o = 1'b1;
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pc_mux_o = PC_EXC;
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exc_pc_mux_o = debug_mode_q ? EXC_PC_DBG_EXC : EXC_PC_EXC;
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csr_save_id_o = 1'b1;
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csr_save_cause_o = 1'b1;
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// set exception registers, priorities according to Table 3.7 of Privileged Spec v1.11
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if (instr_fetch_err_i) begin
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exc_cause_o = EXC_CAUSE_INSTR_ACCESS_FAULT;
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csr_mtval_o = pc_id_i;
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end else if (illegal_insn_i) begin
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exc_cause_o = EXC_CAUSE_ILLEGAL_INSN;
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csr_mtval_o = instr_is_compressed_i ? {16'b0, instr_compressed_i} : instr_i;
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end else if (ecall_insn_i) begin
|
||
exc_cause_o = EXC_CAUSE_ECALL_MMODE;
|
||
|
||
end else if (ebrk_insn_i) begin
|
||
if (debug_mode_q) begin
|
||
/*
|
||
* EBREAK in debug mode re-enters debug mode
|
||
*
|
||
* "The only exception is EBREAK. When that is executed in Debug
|
||
* Mode, it halts the hart again but without updating dpc or
|
||
* dcsr." [Debug Spec v0.13.2, p.39]
|
||
*/
|
||
pc_set_o = 1'b0;
|
||
csr_save_id_o = 1'b0;
|
||
csr_save_cause_o = 1'b0;
|
||
ctrl_fsm_ns = DBG_TAKEN_ID;
|
||
end else if (debug_ebreakm_i) begin
|
||
/*
|
||
* dcsr.ebreakm == 1:
|
||
* "EBREAK instructions in M-mode enter Debug Mode."
|
||
* [Debug Spec v0.13.2, p.42]
|
||
*/
|
||
pc_set_o = 1'b0;
|
||
csr_save_id_o = 1'b0;
|
||
csr_save_cause_o = 1'b0;
|
||
ctrl_fsm_ns = DBG_TAKEN_ID;
|
||
end else begin
|
||
/*
|
||
* "The EBREAK instruction is used by debuggers to cause control
|
||
* to be transferred back to a debugging environment. It
|
||
* generates a breakpoint exception and performs no other
|
||
* operation. [...] ECALL and EBREAK cause the receiving
|
||
* privilege mode’s epc register to be set to the address of the
|
||
* ECALL or EBREAK instruction itself, not the address of the
|
||
* following instruction." [Privileged Spec v1.11, p.40]
|
||
*/
|
||
exc_cause_o = EXC_CAUSE_BREAKPOINT;
|
||
end
|
||
|
||
end else if (store_err_q) begin
|
||
exc_cause_o = EXC_CAUSE_STORE_ACCESS_FAULT;
|
||
csr_mtval_o = lsu_addr_last_i;
|
||
|
||
end else if (load_err_q) begin
|
||
exc_cause_o = EXC_CAUSE_LOAD_ACCESS_FAULT;
|
||
csr_mtval_o = lsu_addr_last_i;
|
||
end
|
||
|
||
end else begin
|
||
// special instructions and pipeline flushes
|
||
if (mret_insn_i) begin
|
||
pc_mux_o = PC_ERET;
|
||
pc_set_o = 1'b1;
|
||
csr_restore_mret_id_o = 1'b1;
|
||
if (nmi_mode_q) begin
|
||
nmi_mode_d = 1'b0; // exit NMI mode
|
||
end
|
||
end else if (dret_insn_i) begin
|
||
pc_mux_o = PC_DRET;
|
||
pc_set_o = 1'b1;
|
||
debug_mode_d = 1'b0;
|
||
end else if (wfi_insn_i) begin
|
||
ctrl_fsm_ns = WAIT_SLEEP;
|
||
end else if (csr_pipe_flush_i && handle_irq) begin
|
||
// start handling IRQs when doing CSR-related pipeline flushes
|
||
ctrl_fsm_ns = IRQ_TAKEN;
|
||
end
|
||
end // exc_req
|
||
|
||
// single stepping
|
||
// set exception registers, but do not jump into handler [Debug Spec v0.13.2, p.44]
|
||
if (debug_single_step_i && !debug_mode_q) begin
|
||
pc_set_o = 1'b0;
|
||
ctrl_fsm_ns = DBG_TAKEN_IF;
|
||
end
|
||
end // FLUSH
|
||
|
||
default: begin
|
||
instr_req_o = 1'b0;
|
||
ctrl_fsm_ns = ctrl_fsm_e'(1'bX);
|
||
end
|
||
endcase
|
||
end
|
||
|
||
///////////////////
|
||
// Stall control //
|
||
///////////////////
|
||
|
||
// if high, current instr needs at least one more cycle to finish after the current cycle
|
||
// if low, current instr finishes in current cycle
|
||
// multicycle instructions have this set except during the last cycle
|
||
assign stall = stall_lsu_i | stall_multdiv_i | stall_jump_i | stall_branch_i;
|
||
|
||
// signal to IF stage that ID stage is ready for next instr
|
||
assign id_in_ready_o = ~stall & ~halt_if;
|
||
|
||
// kill instr in IF-ID pipeline reg that are done, or if a
|
||
// multicycle instr causes an exception for example
|
||
assign instr_valid_clear_o = ~stall | halt_id;
|
||
|
||
// update registers
|
||
always_ff @(posedge clk_i or negedge rst_ni) begin : update_regs
|
||
if (!rst_ni) begin
|
||
ctrl_fsm_cs <= RESET;
|
||
nmi_mode_q <= 1'b0;
|
||
debug_mode_q <= 1'b0;
|
||
load_err_q <= 1'b0;
|
||
store_err_q <= 1'b0;
|
||
end else begin
|
||
ctrl_fsm_cs <= ctrl_fsm_ns;
|
||
nmi_mode_q <= nmi_mode_d;
|
||
debug_mode_q <= debug_mode_d;
|
||
load_err_q <= load_err_d;
|
||
store_err_q <= store_err_d;
|
||
end
|
||
end
|
||
|
||
endmodule
|