This commit clarifies why CSR-related pipeline flushes are needed
(e.g. when enabling interrupts), only introduces them when doing the
critical modifications (write/set bits in `mstatus` and `mie` CSRs
for enabling interrupts, reads and clears are uncritical for these
CSRs), and makes sure the controller is actually able to start
handling interrupts while doing a CSR-related pipeline flush.
This resolveslowrisc/ibex#6.
- Add required signals to top-level
- Propagate error through fetch stages
- Add new exception type
- Update documentation for new exception type
- Resolves issue #109
This commit adds 15 local fast interrupt lines managed through
the `mie` and `mip` CSRs directly, and removes the old legacy
interrupts including the internal controller.
This commit adds the `mip` and `mie` CSRs as well as the software,
timer and external interrupts.
Currently these interrupts are overlapped with some of the legacy
interrupts, i.e., the core will jump to the same address for different
interrupts. For example, the software interrupt has the same ID as
legacy interrupt #3. Thus, the handler must read the `mip` register
to find out whether the interrupt routine has been entered because of
the software interrupt or the legacy interrupt.
Eventually, the number of legacy interrupts will be reduced to avoid
this overlapping, and they will be connected to the `mie` and `mip`
CSRs directly.
This file doesn't contain defines any more, but a normal SV package.
The diff is best viewed without whitespace changes, as the reindents
cause a lof of diff noise.
Fixeslowrisc/ibex#173
This commit changes the controller to save the PC of the next
instruction to the dpc CSR when entering debug mode upon a halt
request instead of the PC of the current instruction (only valid
for EBREAK instructions).
This bug was reported by @taoliug. This resolves#164.
The RVFI implementation make use of signals from the decoder and
controller to detect the state of the processor.
Especially the signal for a new and retired instruction.
* Controller: remove impossible condition for `DBG_TAKEN_IF`
There is no way to jump into `DBG_TAKEN_IF` because of an EBREAK
instruction. Thus, this case also does not need to be checked.
* Controller: do not enter debug when `debug_req_i` goes low
With this commit, the core is prevented from entering debug mode when
the debug request signal is deasserted during that procedure.
Previously, the core would still enter debug mode but not updating the
debug CSR.
This resolves#153 reported by @taoliug.
* Update ibex_controller.sv
The FSM now uses input signals for interrupt and debug request handling
that depend on whether the core is in debug mode. This avoids the need
for many `debug_mode_q` guards and somewhat simplifies the FSM.
If in debug mode, the core shall not handle interrupts according to the
spec anyway.
Once the core is executing, the IF stage now only gets two signals
from the controller: One to clear the instruction valid output and one
to prevent the IF stage from pushing new instructions.
The former `if_valid_o` of the IF stage has been renamed to clarify
that this is not a valid bit but just the write enable for the
pipeline register.
The register file shall not be written upon illegal CSR operations
and when the core is idle (waiting for new instructions). Otherwise
the write enable signal from the WB FSM/decoder is used.
Single stepping should execute exactly one more instruction, not abort
any running (multicycle) instructions, and only enter debug mode after
the current instruction is finished. In case the current instruction
leads to an exception, the exception registers must be set accordingly,
but the core must jump into debug mode instead of the exception
handler.
Previous to this commit, single stepping would immediately jump into
debug mode and ignore any exceptions.
This commit makes sure that interrupts and debug requests do not
interrupt currently running multicycle instructions. Priority is
given 1) to the currently running instruction, possible exceptions
caused by this instruction, 2) debug requests, 3) interrupt
requests.
Previously, currently running instructions were aborted upon
incoming debug and interrupt requests, which could corrupt the
processor state and lead to exceptions being ignored.
This commit resolves#108 and #121.
For exceptions, the Ibex always jumps to the trap vector base address
specified in `mtvec`. The exception cause is specified in `mcause` with
possibly additional information in `mtval`.
Interrupts are handled in vectored mode as before.
`mtval` can provide additional information to trap handlers.
In case of load/store errors, it holds the failing address.
For illegal instruction exceptions, it holds the illegal instruction.
This operation only depends on the LSU detecting a misaligned address.
Previously, the mux control was scattered across ID stage, controller
and decoder. With this commit, all the relevant code for this operation
is moved into the ID stage and also streamlined.
This commit simplifies the assignment of literals to enum types in
default cases by:
- defining or using existing enum values for all-zero values,
- feeding a single `1'bX` into the type cast instead of exact width
(the tools are fine with that).
This commit adds a `default` to all `unique case` statements. Also, in case
FSMs reach an undefined state, the `'X` is propagated to ease detection
in simulation. Both these changes are required by our coding guidelines.
In case of interrupts, `exc_cause` carries the interrupt ID in the lower
bits and its MSB is 0 anyway. There is no need to forward only the lower
bits to the IF stage.
- Move ibex_tracer_defines.sv and ibex_defines.sv out of the 'include'
directory, since these files are not actually included.
- Remove ibex_config.sv, it's mostly unused code. The remaining defines,
SYNTHESIS, ASIC_SYNTHESIS, TRACE_EXECUTION, and CHECK_MISALIGNED should
be set through command-line flags to the simulation/synthesis tools.
Initial version by Nils Gräf.
The code base made extensive use of ASCII art headings/subheadings in
comments to delineate code. Switch to a more space efficient and easier
to edit format:
/////////
// Foo //
/////////
This commit updates the RISC-V debug spec-compliant debug implementation
by incorporating changes mostly done by Robert Balas on the RI5CY core.
Most notably, single stepping works after this patch is applied.
With this patch the RISC-V debug compliance test built into OpenOCD
passes fully.
If an illegal instruction is executed we display a message in
simulation. This message now also contains the instruction itself, not
only the program counter.
This commit switches the ibex core from a custom debug system to an
execution-based, standard RISC-V debug system. The port is based on a
port done for the RI5CY core.
This change has been informed by advice from the lowRISC legal
committee.
The Solderpad 0.51 license states "the Licensor permits any Work
licensed under this License, at the option of the Licensee, to be
treated as licensed under the Apache License Version 2.0". We use this
freedom to convert license markings to Apache 2.0. This commit ensures
that we retain all authorship and copyright attribution information.
