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https://github.com/lowRISC/ibex.git
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- Add required signals to top-level - Propagate error through fetch stages - Add new exception type - Update documentation for new exception type - Resolves issue #109
183 lines
4.7 KiB
Systemverilog
183 lines
4.7 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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/**
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* Top level module of the ibex RISC-V core with tracing enabled
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*/
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module ibex_core_tracing #(
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parameter int unsigned MHPMCounterNum = 8,
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parameter int unsigned MHPMCounterWidth = 40,
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parameter bit RV32E = 0,
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parameter bit RV32M = 1,
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parameter int unsigned DmHaltAddr = 32'h1A110800,
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parameter int unsigned DmExceptionAddr = 32'h1A110808
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) (
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// Clock and Reset
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input logic clk_i,
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input logic rst_ni,
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input logic test_en_i, // enable all clock gates for testing
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// Core ID, Cluster ID and boot address are considered more or less static
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input logic [ 3:0] core_id_i,
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input logic [ 5:0] cluster_id_i,
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input logic [31:0] boot_addr_i,
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// Instruction memory interface
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output logic instr_req_o,
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input logic instr_gnt_i,
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input logic instr_rvalid_i,
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output logic [31:0] instr_addr_o,
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input logic [31:0] instr_rdata_i,
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input logic instr_err_i,
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// Data memory interface
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output logic data_req_o,
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input logic data_gnt_i,
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input logic data_rvalid_i,
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output logic data_we_o,
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output logic [3:0] data_be_o,
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output logic [31:0] data_addr_o,
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output logic [31:0] data_wdata_o,
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input logic [31:0] data_rdata_i,
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input logic data_err_i,
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// Interrupt inputs
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input logic irq_software_i,
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input logic irq_timer_i,
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input logic irq_external_i,
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input logic [14:0] irq_fast_i,
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input logic irq_nm_i, // non-maskeable interrupt
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// Debug Interface
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input logic debug_req_i,
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// CPU Control Signals
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input logic fetch_enable_i
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);
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import ibex_pkg::*;
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// ibex_tracer relies on the signals from the RISC-V Formal Interface
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`ifndef RVFI
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Fatal error: RVFI needs to be defined globally.
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`endif
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logic rvfi_valid;
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logic [63:0] rvfi_order;
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logic [31:0] rvfi_insn;
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logic [31:0] rvfi_insn_uncompressed;
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logic rvfi_trap;
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logic rvfi_halt;
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logic rvfi_intr;
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logic [ 1:0] rvfi_mode;
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logic [ 4:0] rvfi_rs1_addr;
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logic [ 4:0] rvfi_rs2_addr;
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logic [31:0] rvfi_rs1_rdata;
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logic [31:0] rvfi_rs2_rdata;
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logic [ 4:0] rvfi_rd_addr;
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logic [31:0] rvfi_rd_wdata;
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logic [31:0] rvfi_pc_rdata;
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logic [31:0] rvfi_pc_wdata;
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logic [31:0] rvfi_mem_addr;
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logic [ 3:0] rvfi_mem_rmask;
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logic [ 3:0] rvfi_mem_wmask;
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logic [31:0] rvfi_mem_rdata;
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logic [31:0] rvfi_mem_wdata;
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ibex_core #(
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.MHPMCounterNum(MHPMCounterNum),
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.MHPMCounterWidth(MHPMCounterWidth),
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.RV32E(RV32E),
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.RV32M(RV32M),
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.DmHaltAddr(DmHaltAddr),
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.DmExceptionAddr(DmExceptionAddr)
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) u_ibex_core (
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.clk_i,
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.rst_ni,
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.test_en_i,
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.core_id_i,
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.cluster_id_i,
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.boot_addr_i,
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.instr_req_o,
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.instr_gnt_i,
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.instr_rvalid_i,
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.instr_addr_o,
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.instr_rdata_i,
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.instr_err_i,
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.data_req_o,
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.data_gnt_i,
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.data_rvalid_i,
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.data_we_o,
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.data_be_o,
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.data_addr_o,
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.data_wdata_o,
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.data_rdata_i,
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.data_err_i,
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.irq_software_i,
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.irq_timer_i,
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.irq_external_i,
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.irq_fast_i,
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.irq_nm_i,
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.debug_req_i,
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.rvfi_valid,
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.rvfi_order,
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.rvfi_insn,
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.rvfi_insn_uncompressed,
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.rvfi_trap,
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.rvfi_halt,
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.rvfi_intr,
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.rvfi_mode,
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.rvfi_rs1_addr,
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.rvfi_rs2_addr,
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.rvfi_rs1_rdata,
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.rvfi_rs2_rdata,
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.rvfi_rd_addr,
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.rvfi_rd_wdata,
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.rvfi_pc_rdata,
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.rvfi_pc_wdata,
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.rvfi_mem_addr,
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.rvfi_mem_rmask,
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.rvfi_mem_wmask,
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.rvfi_mem_rdata,
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.rvfi_mem_wdata,
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.fetch_enable_i
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);
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`ifndef VERILATOR
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ibex_tracer u_ibex_tracer (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.fetch_enable_i ( fetch_enable_i ),
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.core_id_i ( core_id_i ),
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.cluster_id_i ( cluster_id_i ),
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.valid_i ( rvfi_valid ),
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.pc_i ( rvfi_pc_rdata ),
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.instr_i ( rvfi_insn_uncompressed ),
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.rs1_value_i ( rvfi_rs1_rdata ),
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.rs2_value_i ( rvfi_rs2_rdata ),
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.ex_reg_addr_i ( rvfi_rd_addr ),
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.ex_reg_wdata_i ( rvfi_rd_wdata ),
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.ex_data_addr_i ( rvfi_mem_addr ),
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.ex_data_wdata_i ( rvfi_mem_wdata ),
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.ex_data_rdata_i ( rvfi_mem_rdata )
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);
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`else
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// ibex_tracer uses language constructs which Verilator doesn't understand.
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`endif
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endmodule
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