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ibex_alu.sv
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[rtl] Add memory and memory result interfaces
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2023-03-31 15:29:50 +02:00 |
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ibex_branch_predict.sv
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Fix Xcelium warnings
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2020-11-18 10:16:48 +00:00 |
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ibex_compressed_decoder.sv
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[style] Indent module header with two spaces
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2021-08-31 15:30:28 +02:00 |
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ibex_controller.sv
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[rtl] Add issue, commit, and result interfaces
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2022-10-04 12:10:51 +02:00 |
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ibex_core.f
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[rtl] Add issue, commit, and result interfaces
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2022-10-04 12:10:51 +02:00 |
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ibex_core.sv
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[test] Connect FPU subsystem
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2023-03-31 15:58:32 +02:00 |
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ibex_counter.sv
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[rtl] Fix retired instruction counters
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2021-09-17 12:28:10 +01:00 |
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ibex_cs_registers.sv
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[rtl] Performance Counters
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2023-03-31 15:29:50 +02:00 |
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ibex_csr.sv
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[style] Indent module header with two spaces
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2021-08-31 15:30:28 +02:00 |
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ibex_decoder.sv
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[rtl] Add issue, commit, and result interfaces
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2022-10-04 12:10:51 +02:00 |
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ibex_dummy_instr.sv
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[rtl] Add SEC_CM markers for security features
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2022-03-09 08:57:24 +00:00 |
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ibex_ex_block.sv
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[rtl] Add memory and memory result interfaces
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2023-03-31 15:29:50 +02:00 |
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ibex_fetch_fifo.sv
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Move NT branch addr calculation to ID stage
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2021-11-18 13:05:19 +00:00 |
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ibex_icache.sv
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[rtl] Remove "mispredict" ports from icache
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2022-04-04 16:56:04 +01:00 |
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ibex_id_stage.sv
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[rtl] Performance Counters
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2023-03-31 15:29:50 +02:00 |
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ibex_if_stage.sv
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[rtl] Performance Counters
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2023-03-31 15:29:50 +02:00 |
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ibex_load_store_unit.sv
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[rtl] Add memory and memory result interfaces
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2023-03-31 15:29:50 +02:00 |
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ibex_lockstep.sv
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[rtl] Add memory and memory result interfaces
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2023-03-31 15:29:50 +02:00 |
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ibex_multdiv_fast.sv
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[rtl] Add SEC_CM markers for security features
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2022-03-09 08:57:24 +00:00 |
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ibex_multdiv_slow.sv
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[rtl] Add SEC_CM markers for security features
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2022-03-09 08:57:24 +00:00 |
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ibex_pkg.sv
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[rtl] Add memory and memory result interfaces
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2023-03-31 15:29:50 +02:00 |
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ibex_pmp.sv
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[fcov] Add and improve functional coverage
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2022-03-28 14:53:27 +01:00 |
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ibex_pmp_reset_default.svh
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[rtl,doc] Add customisable PMP reset values
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2022-01-24 10:01:36 +00:00 |
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ibex_prefetch_buffer.sv
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[rtl] Remove "mispredict" ports from prefetch buffer
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2022-04-04 16:56:04 +01:00 |
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ibex_register_file_ff.sv
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[rtl] Add SEC_CM markers for security features
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2022-03-09 08:57:24 +00:00 |
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ibex_register_file_fpga.sv
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[rtl] Replace always_ff with always @(posedge .. in FPGA regfile
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2021-12-09 16:35:31 +01:00 |
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ibex_register_file_latch.sv
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[rtl] Add SEC_CM markers for security features
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2022-03-09 08:57:24 +00:00 |
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ibex_top.sv
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[rtl] Add memory and memory result interfaces
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2023-03-31 15:29:50 +02:00 |
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ibex_top_tracing.sv
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[rtl] Add memory and memory result interfaces
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2023-03-31 15:29:50 +02:00 |
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ibex_tracer.sv
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[test] Connect FPU subsystem
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2023-03-31 15:58:32 +02:00 |
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ibex_tracer_pkg.sv
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[test] Connect FPU subsystem
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2023-03-31 15:58:32 +02:00 |
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ibex_wb_stage.sv
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[rtl] Add memory and memory result interfaces
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2023-03-31 15:29:50 +02:00 |
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ibex_xif_issue_commit_buffer.sv
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[rtl] Add memory and memory result interfaces
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2023-03-31 15:29:50 +02:00 |
