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72 lines
2 KiB
Markdown
72 lines
2 KiB
Markdown
# Ibex RISC-V Core SoC Example
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Please see [examples](https://ibex-core.readthedocs.io/en/latest/examples.html "Ibex User Manual") for a description of this example.
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## Requirements
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### Tools
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- RV32 compiler
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- srecord
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- `fusesoc` and its dependencies
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- Xilinx Vivado
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### Hardware
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- Either a Digilent Arty A7-35 oder A7-100 board
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## Build
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The easiest way to build and execute this example is to call the following make goals from the root directory.
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Use the following for the Arty A7-35
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```
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make build-arty-35 program-arty
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```
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and for the Arty A7-100
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```
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make build-arty-100 program-arty
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```
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### Software
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First the software must be built. Go into `examples/sw/led` and call:
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```
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make CC=/path/to/RISC-V-compiler
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```
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The setting of `CC` is only required if `riscv32-unknown-elf-gcc` is not available through the `PATH` environment variable.
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The path to the RV32 compiler `/path/to/RISC-V-compiler` depends on the environment.
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For example, it can be for example `/opt/riscv/bin/riscv-none-embed-gcc` if the whole path is required or simply the name of the executable if it is available through the `PATH` environment variable.
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This should produce a `led.vmem` file which is used in the synthesis to update the SRAM storage.
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### Hardware
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Run either of the following commands at the top level to build the respective hardware.
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Both variants of the Arty A7 are supported and can be selected via the `--parts` parameter.
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```
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fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7 --part xc7a35ticsg324-1L
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```
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```
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fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7 --part xc7a100tcsg324-1
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```
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This will create a directory `build` which contains the output files, including
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the bitstream.
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## Program
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After the board is connected to the computer it can be programmed with:
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```
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fusesoc --cores-root=. run --target=synth --run lowrisc:ibex:top_artya7
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```
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LED1/LED3 and LED0/LED2 should alternately be on after the FPGA programming is finished.
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