Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
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Rupert Swarbrick 08fc2a4af6 Various cleanups in sim.py's rtl_sim function
This is a bit more verbose, but I think it's a bit more obvious what's
going on, and quite a lot of the added lines are docstrings explaining
the code.

We now split "find the list of commands to run" from "run the
commands" with or without LSF.

The other major change is that the --lsf_cmd parameter defaults to
None, rather than the empty string. The patch also updates the
Makefile accordingly.

Finally, since we're now a little more careful with passing paths
around, we don't have to change cwd for each run. I'm not convinced
that the LSF mode actually worked before, since we needed to run each
command in a different directory. It should probably work now, but I
don't have access to LSF to check.

The only sad thing is that UVM leaves a 'tr_db.log' file lying around
in the current directory. I don't think we really care about the
contents, but can't see how to disable it, so I've added it to
gitignore.
2020-03-10 09:16:16 +00:00
doc [I-Cache] Initial commit of prototype RTL 2020-03-06 16:34:48 +00:00
dv Various cleanups in sim.py's rtl_sim function 2020-03-10 09:16:16 +00:00
examples [sw] Add Coremark makefile and support files 2020-03-09 14:41:40 +00:00
lint Merge pull request #624 from ganoam/fpga-opt-perf-mon-pr 2020-03-06 12:49:51 +01:00
rtl [I-Cache] Initial commit of prototype RTL 2020-03-06 16:34:48 +00:00
shared Make exiting from simple_system tests work with Spike 2020-03-02 15:45:47 +00:00
syn [syn] Synthesis fixes 2020-03-09 15:08:10 +00:00
util Check for supported tool versions 2020-02-12 15:57:40 +00:00
vendor Update google_riscv-dv to google/riscv-dv@3f584ad (#676) 2020-03-09 18:55:17 -07:00
.clang-format Add lowRISC standard clang-format file 2019-09-11 12:00:49 +01:00
.gitignore Various cleanups in sim.py's rtl_sim function 2020-03-10 09:16:16 +00:00
azure-pipelines.yml [ci] Fix removal of vendored files from C/C++ lint 2020-03-09 14:41:40 +00:00
check_tool_requirements.core Check for supported tool versions 2020-02-12 15:57:40 +00:00
CONTRIBUTING.md Fix vim setting suggestion 2019-06-19 14:39:41 +02:00
CREDITS.md Add Greg Chadwick to CREDITS.md 2019-10-17 11:07:05 +01:00
ibex_core.core [RTL] Add configurable third pipeline stage 2020-03-06 15:29:14 +00:00
ibex_core_tracing.core [RTL] Added seperate ALU for branch target 2020-01-31 09:32:20 +00:00
ibex_tracer.core [rtl] Remove X assignments, add SVAs for selector signals 2019-12-20 10:09:09 +01:00
LICENSE Convert from Solderpad to standard Apache 2.0 license 2019-04-26 15:05:17 +01:00
Makefile Fix FPGA part number for Arty A7-100T 2020-02-02 11:47:59 +01:00
README.md [ci] Add clang-format checking to CI 2020-01-02 13:20:35 +01:00
src_files.yml Fix incdirs of src_files.yml 2020-02-03 08:33:11 +00:00
tool_requirements.py Switch Verilator linter to matches 2020-03-02 12:01:10 +00:00

Build Status

Ibex RISC-V Core

Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture.

Ibex offers several configuration parameters to meet the needs of various application scenarios. The options include two different choices for the architecture of the multiplier and divider unit, as well as the possibility to drop the support for the "M" extension completely. In addition, the "E" extension can be enabled when opting for a minimum-area configuration.

This core was initially developed as part of the PULP platform under the name "Zero-riscy" [1], and has been contributed to lowRISC who maintains it and develops it further. It is under active development, with further code cleanups, feature additions, and test and verification planned for the future.

Documentation

The Ibex user manual can be read online at ReadTheDocs. It is also contained in the doc folder of this repository.

Contributing

We highly appreciate community contributions. To ease our work of reviewing your contributions, please:

  • Create your own branch to commit your changes and then open a Pull Request.
  • Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
  • Write meaningful commit messages. For more information, please check out the contribution guide.
  • If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.

When contributing SystemVerilog source code, please try to be consistent and adhere to our Verilog coding style guide.

When contributing C or C++ source code, please try to adhere to the OpenTitan C++ coding style guide. All C and C++ code should be formatted with clang-format before committing. Either run clang-format -i filename.cc or git clang-format on added files.

To get started, please check out the "Good First Issue" list.

Issues and Troubleshooting

If you find any problems or issues with Ibex or the documentation, please check out the issue tracker and create a new issue if your problem is not yet tracked.

Questions?

Do not hesitate to contact us, e.g., on our public Ibex channel on Zulip!

License

Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).

Credits

Many people have contributed to Ibex through the years. Please have a look at the credits file and the commit history for more information.

References

  1. Schiavone, Pasquale Davide, et al. "Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications." 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017)