409892ec8c
- Decoding must give precedence to rs2 (i.e. instr_i[6:2]) to switch between C.MV and C.JR. "C.MV is only valid when rs2̸=x0; the code points with rs2=x0 correspond to the C.JR instruction. The code points with rs2̸=x0 and rd=x0 are HINTs." - C.JR is only valid with rs1==x0. Throw an illegal instruction exception if that's not the case. "C.JR is only valid when rs1̸=x0; the code point with rs1=x0 is reserved." RV32 Spec, p103 All spec references based on RISC-V Unprivileged ISA V20190305-Base-Ratification |
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| doc | ||
| rtl | ||
| .gitignore | ||
| ibex.core | ||
| ibex_tracer.core | ||
| LICENSE | ||
| README.md | ||
| src_files.yml | ||
Ibex: RISC-V Core
Ibex is a small 32 bit RISC-V core with a 2-stage pipeline.
Ibex fully implements the RV32IMC instruction set and a small set of RISC-V privileged specifications. Ibex can be configured to be very small by disabling the RV32M extensions and by activating the RV32E extensions.
This core was initially developed as part of the PULP platform under the name "Zero-riscy", and has been contributed to lowRISC who maintains it and develops it further.
Ibex is under active development, with further code cleanups, feature additions, and test and verification planned for the future.
Documentation
The Ibex documentation can be read online at ReadTheDocs.
It is also contained in the doc folder of this repository.
We highly appreciate pull requests on the documentation if you find anything wrong or outdated!
License
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).