Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

cpucorehardwarerisc-vrv32

Sven Stucki 57edf30a46 Minor controller cleanup		2015-07-28 15:04:28 +02:00
include	Added post increment loads, reg-reg loads and post-increment reg-reg loads	2015-07-28 14:58:14 +02:00
.gitignore	Added vim swap file	2015-07-24 15:26:32 +02:00
alu.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
compressed_decoder.sv	Four more compressed instructions	2015-07-24 18:24:18 +02:00
controller.sv	Minor controller cleanup	2015-07-28 15:04:28 +02:00
cs_registers.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
debug_unit.sv	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00
ex_stage.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
exc_controller.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
id_stage.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
if_stage.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
instr_core_interface.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
load_store_unit.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
mult.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
register_file.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
riscv_core.sv	Added post increment loads, reg-reg loads and post-increment reg-reg loads	2015-07-28 14:58:14 +02:00
wb_stage.sv	Updated all file headers	2015-07-24 15:26:12 +02:00