Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
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Rupert Swarbrick 717cb90aef Rework choosing new seeds in icache UVM memory model
The flow for a memory fetch is:

  1. Cache requests data for a memory address
  2. Agent spots the request, maybe signalling a PMP error
  3. Grant line goes high, at which point the request is granted.
  4. Sometime later (in-order pipeline), agent sends a response

Occasionally, we need to pick a new seed for the backing memory.
Before this patch, we picked these seeds at point (3).

Unfortunately this was wrong in the following case:

  1. We're switching from seed S0 to seed S1.
  2. The request is spotted with seed S0 and doesn't signal a PMP error
  3. The request is granted and we switch to seed S1.
  4. We respond with data from memory based on S1, with no memory
     error either

If S1 would have caused a PMP error, the resulting fetch (no error,
but data from S1) doesn't match any possible seed and the scoreboard
gets confused.

This patch changes to picking new seeds at (2) to solve the problem.
This isn't quite enough by itself, because if a request is granted on
a clock-edge, a new request address might appear and there isn't a
guaranteed ordering in the simulation between the new request and the
old grant (both things happen at the same time). To fix this, the
response sequence now maintains a queue of requests and their
corresponding seeds to make sure that all the checks for a fetch are
done with a single seed.

The patch also gets rid of the seed state in the memory model: it
turns out that this didn't really help: the scoreboard is always
asking "what would I get with this seed?" and now the sequence is
doing something similar.
2020-05-04 09:57:30 +01:00
ci [ci] Fix multi-config CI 2020-04-14 15:08:00 +01:00
doc [doc] Minor fixes 2020-05-01 20:09:59 +02:00
dv Rework choosing new seeds in icache UVM memory model 2020-05-04 09:57:30 +01:00
examples Add RV32B parameter option 2020-04-24 14:58:12 +02:00
lint [bitmanip] Add ZBS Instruction Group 2020-04-24 08:32:30 +02:00
rtl [rtl] icache error signalling fix 2020-05-04 09:16:55 +01:00
shared [dv] Fix Xcelium compilation 2020-04-25 17:59:32 +01:00
syn [syn] Place result directories in sub-directory 2020-03-12 13:44:09 +00:00
util Teach check_tool_requirements to check for edalize versions 2020-04-16 09:38:38 +01:00
vendor Update dvsim to lowRISC/opentitan@1d17b122 2020-04-28 17:42:02 +01:00
.clang-format Add lowRISC standard clang-format file 2019-09-11 12:00:49 +01:00
.gitignore Ignore modelsim.ini generated from Questa tool 2020-03-13 10:58:53 +00:00
azure-pipelines.yml CI: Use packaged version of Verilator 2020-04-21 11:09:23 +01:00
check_tool_requirements.core Check for supported tool versions 2020-02-12 15:57:40 +00:00
CONTRIBUTING.md Fix vim setting suggestion 2019-06-19 14:39:41 +02:00
CREDITS.md Add Greg Chadwick to CREDITS.md 2019-10-17 11:07:05 +01:00
ibex_configs.yaml Switch from 'bool' to 'int' parameters in fusesoc core files 2020-04-14 15:30:26 +01:00
ibex_core.core Switch from 'bool' to 'int' parameters in fusesoc core files 2020-04-14 15:30:26 +01:00
ibex_core_tracing.core Switch from 'bool' to 'int' parameters in fusesoc core files 2020-04-14 15:30:26 +01:00
ibex_icache.core [dv] initial icache testbench (#711) 2020-03-27 11:02:47 -07:00
ibex_pkg.core Factor out ibex_pkg.sv into a separate core file 2020-03-27 10:44:09 +00:00
ibex_tracer.core Factor out ibex_pkg.sv into a separate core file 2020-03-27 10:44:09 +00:00
LICENSE Convert from Solderpad to standard Apache 2.0 license 2019-04-26 15:05:17 +01:00
Makefile [ci] Introduce multiple-configuration CI 2020-03-27 10:30:46 +00:00
python-requirements.txt Add Verible lint as one lint option 2020-03-16 16:54:41 +00:00
README.md [ci] Add clang-format checking to CI 2020-01-02 13:20:35 +01:00
src_files.yml Update src_files.yml 2020-04-23 15:44:56 +02:00
tool_requirements.py Teach check_tool_requirements to check for edalize versions 2020-04-16 09:38:38 +01:00

Build Status

Ibex RISC-V Core

Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture.

Ibex offers several configuration parameters to meet the needs of various application scenarios. The options include two different choices for the architecture of the multiplier and divider unit, as well as the possibility to drop the support for the "M" extension completely. In addition, the "E" extension can be enabled when opting for a minimum-area configuration.

This core was initially developed as part of the PULP platform under the name "Zero-riscy" [1], and has been contributed to lowRISC who maintains it and develops it further. It is under active development, with further code cleanups, feature additions, and test and verification planned for the future.

Documentation

The Ibex user manual can be read online at ReadTheDocs. It is also contained in the doc folder of this repository.

Contributing

We highly appreciate community contributions. To ease our work of reviewing your contributions, please:

  • Create your own branch to commit your changes and then open a Pull Request.
  • Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
  • Write meaningful commit messages. For more information, please check out the contribution guide.
  • If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.

When contributing SystemVerilog source code, please try to be consistent and adhere to our Verilog coding style guide.

When contributing C or C++ source code, please try to adhere to the OpenTitan C++ coding style guide. All C and C++ code should be formatted with clang-format before committing. Either run clang-format -i filename.cc or git clang-format on added files.

To get started, please check out the "Good First Issue" list.

Issues and Troubleshooting

If you find any problems or issues with Ibex or the documentation, please check out the issue tracker and create a new issue if your problem is not yet tracked.

Questions?

Do not hesitate to contact us, e.g., on our public Ibex channel on Zulip!

License

Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).

Credits

Many people have contributed to Ibex through the years. Please have a look at the credits file and the commit history for more information.

References

  1. Schiavone, Pasquale Davide, et al. "Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications." 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017)