Robert Schilling a3865e6cd0 [ibex,tracer] Uniquify trace log with module hierarchy ... In case of having multiple Ibexes, this caues a conflict in openening the same filename from different instances. Add the unique module hierarchy into the filename. Signed-off-by: Robert Schilling <rschilling@rivosinc.com>		2025-02-14 09:18:18 +01:00
..
ibex_alu.sv	[lint] Minor fixes	2022-04-12 08:38:35 -07:00
ibex_branch_predict.sv	Fix Xcelium warnings	2020-11-18 10:16:48 +00:00
ibex_compressed_decoder.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_controller.sv	[controller] Add assertion on pipeline flush when entering debug mode	2024-12-19 10:42:48 +00:00
ibex_core.f	Add missing copyright headers	2024-03-28 08:41:30 +00:00
ibex_core.sv	[ibex_core] Fix assertion when SecureIbex is false	2025-01-24 12:49:45 +00:00
ibex_counter.sv	[rtl] Fix non-DSP reset in ibex_counter	2024-12-06 14:55:01 +00:00
ibex_cs_registers.sv	[pmp] Use top-level straps for PMP reset values	2024-09-23 10:28:57 +00:00
ibex_csr.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_decoder.sv	[rtl] Remove redundant comments in decoder	2021-12-16 14:18:00 +01:00
ibex_dummy_instr.sv	[rtl] Add SEC_CM markers for security features	2022-03-09 08:57:24 +00:00
ibex_ex_block.sv	[rtl] Guard against false memory responses for secure configurations	2024-06-04 10:00:34 +00:00
ibex_fetch_fifo.sv	Move NT branch addr calculation to ID stage	2021-11-18 13:05:19 +00:00
ibex_icache.sv	[lint] Make case statements unique case	2022-08-24 15:33:38 -07:00
ibex_id_stage.sv	Fix typo in comment in ibex_id_stage.sv	2025-01-16 19:17:50 +00:00
ibex_if_stage.sv	[rtl] Add missing `include to ibex_if_stage	2023-04-11 14:22:05 +00:00
ibex_load_store_unit.sv	[dv] Various fcov fixes and tweaks	2022-11-16 12:52:33 +00:00
ibex_lockstep.sv	[rtl,pmp] Allow all accesses to Debug Module in debug mode	2024-12-19 10:42:48 +00:00
ibex_multdiv_fast.sv	[rtl] Guard against false memory responses for secure configurations	2024-06-04 10:00:34 +00:00
ibex_multdiv_slow.sv	[rtl] Guard against false memory responses for secure configurations	2024-06-04 10:00:34 +00:00
ibex_pkg.sv	[pmp] Use top-level straps for PMP reset values	2024-09-23 10:28:57 +00:00
ibex_pmp.sv	[rtl,pmp] Allow all accesses to Debug Module in debug mode	2024-12-19 10:42:48 +00:00
ibex_prefetch_buffer.sv	[rtl] Remove "mispredict" ports from prefetch buffer	2022-04-04 16:56:04 +01:00
ibex_register_file_ff.sv	[rtl] Fix FI vulnerability in RF	2024-01-04 15:26:32 +00:00
ibex_register_file_fpga.sv	[ibex_register_file_fpga] Drop two confusing comments	2025-01-23 19:27:35 +00:00
ibex_register_file_latch.sv	[rtl] Fix wrong address in latch RF	2024-09-17 14:25:27 +00:00
ibex_top.sv	[rtl,pmp] Allow all accesses to Debug Module in debug mode	2024-12-19 10:42:48 +00:00
ibex_top_tracing.sv	[rtl,pmp] Allow all accesses to Debug Module in debug mode	2024-12-19 10:42:48 +00:00
ibex_tracer.sv	[ibex,tracer] Uniquify trace log with module hierarchy	2025-02-14 09:18:18 +01:00
ibex_tracer_pkg.sv	[rtl, bitmanip] Add xperm.[nbh] instruction (Zbp, draft v.0.93)	2021-12-06 11:14:49 +01:00
ibex_wb_stage.sv	[rtl] Guard against false memory responses for secure configurations	2024-06-04 10:00:34 +00:00