bbde00d174
Update code from upstream repository https://github.com/lowRISC/opentitan to revision d1be61ba88a145e882df4e7c7a47f78bcf2371f8 * [testplanner] Replace IP milestone terminology with development stage (Michael Schaffner) * [doc] Replace IP milestone terminology with development stage (Michael Schaffner) * [prim] Fix missing case from prim_reg_cdc_arb assert (Timothy Chen) * [tools/dv] Remove set_fsm_reset_scoring coverage directive from common.ccf (Steve Nelson) * [dv] Exclude FSM transitions that can only happen on reset (Weicai Yang) * [chip dv] Fixes for chip level falures (Srikrishna Iyer) * [dv, mem_bkdr_util] Add system base addr (Srikrishna Iyer) * Switch to run-time options instead (Timothy Chen) * [dvsim] Fix coverage upload URL (Michael Schaffner) * [prim] Tweak code slightly to avoid UNR entries (Timothy Chen) * [prim] Add () to s_eventually (Timothy Chen) * [dvsim] Add python workaround for shutil (Michael Schaffner) * [dvsim] Make sure odir is of type Path (Michael Schaffner) * [dvsim] Fix bug causing error in existing odirs (Canberk Topal) * [prim] More refactoring to remove UNR generation (Timothy Chen) * [dvsim] Fix flake8 lint warnings (Michael Schaffner) * [dvsim] Align local and server path structure (Michael Schaffner) * [dvsim] Remove support for email report (Michael Schaffner) * [dvsim/doc] Place summary results into separate hierarchy (Michael Schaffner) * [dvsim/utils] Fix a typo (Michael Schaffner) * [dvsim] Default report folder name to 'latest' (Michael Schaffner) * [dvsim] Use relative links on summary page (Michael Schaffner) * [xcelium warning] Cleanup unexpected semicolon warning (Srikrishna Iyer) * [dv/mem_bkdr] Fix digest update (Timothy Chen) * [dvsim] Handle same test added twice via `-i` (Srikrishna Iyer) * [lint] Fix shellcheck errors in hw (Miles Dai) * [sw/silicon_creator] Rename mask_rom to rom (Alphan Ulusoy) * [spi_device/dv] Fix payload check (Weicai Yang) * [dvsvim] ensure ELF file with proper ext gets copied to `run_dir` (Timothy Trippel) * [prim] Assertion update for prim_reg_cdc (Timothy Chen) * [prim_lfsr dv] Designate a primary build (Srikrishna Iyer) * [dv] Increase stress tests run time limit to 3h (Weicai Yang) * [dvsim] Fix run timeout override in hjson (Srikrishna Iyer) * [dv/cov] Exclude some prim modules from detailed coverage (Guillermo Maturana) * [prim,dv] Reg CDC hardware request fix (Canberk Topal) * [prim] Add more lint waivers (Michael Schaffner) * [dvsim] Add support for specifying primary_build_mode (Srikrishna Iyer) * [dv] Add some VCS coverage options (Srikrishna Iyer) * feat(kmac): Add FI attack protection on packer pos (Eunchan Kim) * [dv] small fix at mem_model (Weicai Yang) * [dvsim] enable manufacturer tests to run in DV sim (Timothy Trippel) * [dvsim] Fix errors due to test duplication (Srikrishna Iyer) * [pad_wrapper] Do not model keeper (Michael Schaffner) * [lint] Fix several SAME_NAME_TYPE errors (Michael Schaffner) * [flash_ctrl] Lint fix (Michael Schaffner) * [dvsim] Include error message cotext (Srikrishna Iyer) Signed-off-by: Michael Schaffner <msf@google.com> |
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| CONTRIBUTING.md | ||
| CREDITS.md | ||
| ibex_configs.yaml | ||
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| ibex_icache.core | ||
| ibex_multdiv.core | ||
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| ibex_top_tracing.core | ||
| ibex_tracer.core | ||
| LICENSE | ||
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| README.md | ||
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Ibex RISC-V Core
Ibex is a production-quality open source 32-bit RISC-V CPU core written in SystemVerilog. The CPU core is heavily parametrizable and well suited for embedded control applications. Ibex is being extensively verified and has seen multiple tape-outs. Ibex supports the Integer (I) or Embedded (E), Integer Multiplication and Division (M), Compressed (C), and B (Bit Manipulation) extensions.
The block diagram below shows the small parametrization with a 2-stage pipeline.
Ibex was initially developed as part of the PULP platform under the name "Zero-riscy", and has been contributed to lowRISC who maintains it and develops it further. It is under active development.
Configuration
Ibex offers several configuration parameters to meet the needs of various application scenarios. The options include different choices for the architecture of the multiplier unit, as well as a range of performance and security features. The table below indicates performance, area and verification status for a few selected configurations. These are configurations on which lowRISC is focusing for performance evaluation and design verification (see supported configs).
| Config | "micro" | "small" | "maxperf" | "maxperf-pmp-bmfull" |
|---|---|---|---|---|
| Features | RV32EC | RV32IMC, 3 cycle mult | RV32IMC, 1 cycle mult, Branch target ALU, Writeback stage | RV32IMCB, 1 cycle mult, Branch target ALU, Writeback stage, 16 PMP regions |
| Performance (CoreMark/MHz) | 0.904 | 2.47 | 3.13 | 3.13 |
| Area - Yosys (kGE) | 16.85 | 26.60 | 32.48 | 66.02 |
| Area - Commercial (estimated kGE) | ~15 | ~24 | ~30 | ~61 |
| Verification status | Red | Green | Amber | Amber |
Notes:
- Performance numbers are based on CoreMark running on the Ibex Simple System platform. Note that different ISAs (use of B and C extensions) give the best results for different configurations. See the Benchmarks README for more information.
- Yosys synthesis area numbers are based on the Ibex basic synthesis flow using the latch-based register file.
- Commercial synthesis area numbers are a rough estimate of what might be achievable with a commercial synthesis flow and technology library.
- For comparison, the original "Zero-riscy" core yields an area of 23.14kGE using our Yosys synthesis flow.
- Verification status is a rough guide to the overall maturity of a particular configuration. Green indicates that verification is close to complete. Amber indicates that some verification has been performed, but the configuration is still experimental. Red indicates a configuration with minimal/no verification. Users must make their own assessment of verification readiness for any tapeout.
- v.1.0.0 of the RISC-V Bit-Manipulation Extension is supported as well as the remaining sub-extensions of draft v.0.93 of the bitmanip spec. The latter are not ratified and there may be changes before ratification. See Standards Compliance in the Ibex documentation for more information.
Documentation
The Ibex user manual can be
read online at ReadTheDocs. It is also contained in
the doc folder of this repository.
Examples
The Ibex repository includes Simple System. This is an intentionally simple integration of Ibex with a basic system that targets simulation. It is intended to provide an easy way to get bare metal binaries running on Ibex in simulation.
A more complete example can be found in the Ibex Super System repository. In particular it includes a integration of the PULP RISC-V debug module. It targets the Arty A7 FPGA board from Digilent and supports debugging via OpenOCD and GDB over USB (no external JTAG probe required). The Ibex Super System is written by lowRISC but is not an official part of Ibex, nor officially supported by lowRISC.
Contributing
We highly appreciate community contributions. To ease our work of reviewing your contributions, please:
- Create your own branch to commit your changes and then open a Pull Request.
- Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
- Write meaningful commit messages. For more information, please check out the contribution guide.
- If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.
When contributing SystemVerilog source code, please try to be consistent and adhere to our Verilog coding style guide.
When contributing C or C++ source code, please try to adhere to the OpenTitan C++ coding style
guide.
All C and C++ code should be formatted with clang-format before committing.
Either run clang-format -i filename.cc or git clang-format on added files.
To get started, please check out the "Good First Issue" list.
Issues and Troubleshooting
If you find any problems or issues with Ibex or the documentation, please check out the issue tracker and create a new issue if your problem is not yet tracked.
Questions?
Do not hesitate to contact us, e.g., on our public Ibex channel on Zulip!
License
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).
Credits
Many people have contributed to Ibex through the years. Please have a look at the credits file and the commit history for more information.