daro b44f01004a extended x register file with additional read ports		2024-09-24 15:19:24 +03:00
..
ibex_alu.sv	[lint] Minor fixes	2022-04-12 08:38:35 -07:00
ibex_branch_predict.sv	Fix Xcelium warnings	2020-11-18 10:16:48 +00:00
ibex_compressed_decoder.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_controller.sv	[rtl] Remove ECC related data_rdata_i -> instr_X_o feedthroughs	2024-08-23 20:31:14 +00:00
ibex_core.f	Add missing copyright headers	2024-03-28 08:41:30 +00:00
ibex_core.sv	extended x register file with additional read ports	2024-09-24 15:19:24 +03:00
ibex_counter.sv	Add missing copyright headers	2024-03-28 08:41:30 +00:00
ibex_cs_registers.sv	[rtl] Fix MISA X bit for balanced bitmanip config	2023-03-02 10:15:34 +00:00
ibex_csr.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_decoder.sv	modified start-up code, ecall shall end the simulation	2024-09-05 13:31:28 +03:00
ibex_dummy_instr.sv	[rtl] Add SEC_CM markers for security features	2022-03-09 08:57:24 +00:00
ibex_ex_block.sv	[rtl] Guard against false memory responses for secure configurations	2024-06-04 10:00:34 +00:00
ibex_fetch_fifo.sv	Move NT branch addr calculation to ID stage	2021-11-18 13:05:19 +00:00
ibex_icache.sv	refactored isolde/sw/simple_system/common/simple_system_common.c for LLVM compiler	2024-09-17 17:50:32 +03:00
ibex_id_stage.sv	extended x register file with additional read ports	2024-09-24 15:19:24 +03:00
ibex_if_stage.sv	WIP: fetching a batch of instruction, initial FSM for decoding variable length instructions	2024-09-11 16:41:56 +03:00
ibex_load_store_unit.sv	[dv] Various fcov fixes and tweaks	2022-11-16 12:52:33 +00:00
ibex_lockstep.sv	[dv] Update testbench to use new 'pre_val' MIP	2024-07-03 15:31:44 +00:00
ibex_multdiv_fast.sv	[rtl] Guard against false memory responses for secure configurations	2024-06-04 10:00:34 +00:00
ibex_multdiv_slow.sv	[rtl] Guard against false memory responses for secure configurations	2024-06-04 10:00:34 +00:00
ibex_pkg.sv	[rtl] Harden lockstep enable against FI	2024-01-23 09:14:45 +00:00
ibex_pmp.sv	[rtl] Avoid name collision in ibex_pmp.sv	2023-12-05 15:18:40 +00:00
ibex_pmp_reset_default.svh	[rtl,doc] Add customisable PMP reset values	2022-01-24 10:01:36 +00:00
ibex_prefetch_buffer.sv	[rtl] Remove "mispredict" ports from prefetch buffer	2022-04-04 16:56:04 +01:00
ibex_register_file_ff.sv	extended x register file with additional read ports	2024-09-24 15:19:24 +03:00
ibex_register_file_fpga.sv	[rtl] Fix FI vulnerability in RF	2024-01-04 15:26:32 +00:00
ibex_register_file_latch.sv	[rtl] Fix FI vulnerability in RF	2024-01-04 15:26:32 +00:00
ibex_top.sv	extended x register file with additional read ports	2024-09-24 15:19:24 +03:00
ibex_top_tracing.sv	[dv] Update testbench to use new 'pre_val' MIP	2024-07-03 15:31:44 +00:00
ibex_tracer.sv	[tracer] Fix reporting of load/store data	2024-02-17 20:43:01 +00:00
ibex_tracer_pkg.sv	[rtl, bitmanip] Add xperm.[nbh] instruction (Zbp, draft v.0.93)	2021-12-06 11:14:49 +01:00
ibex_wb_stage.sv	[rtl] Guard against false memory responses for secure configurations	2024-06-04 10:00:34 +00:00
isolde_decoder.sv	extended x register file with additional read ports	2024-09-24 15:19:24 +03:00
isolde_decoder_pkg.sv	test case updates	2024-09-21 20:21:30 +03:00
isolde_exec_block.sv	extended x register file with additional read ports	2024-09-24 15:19:24 +03:00
isolde_fetch2exec_if.sv	extended x register file with additional read ports	2024-09-24 15:19:24 +03:00
isolde_fetch_vleninstr.sv	added rtl/isolde_exec_block.sv	2024-09-22 22:40:04 +03:00
isolde_register_file_ff.sv	refactored rtl/isolde_register_file_ff.sv	2024-09-23 17:53:16 +03:00
isolde_register_file_if.sv	extended x register file with additional read ports	2024-09-24 15:19:24 +03:00
isolde_register_file_pkg.sv	initial version of ISOLDE register file	2024-09-19 21:55:40 +03:00
isolde_x_register_file_if.sv	extended x register file with additional read ports	2024-09-24 15:19:24 +03:00