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⚠️ [top] split B ISA extension
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stnolting
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3 changed files with 120 additions and 112 deletions
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@ -196,108 +196,110 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
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|=======================
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| Name | Type | Default | Description
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4+^| **General**
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| `CLOCK_FREQUENCY` | natural | - | The clock frequency of the processor's `clk_i` input port in Hertz (Hz).
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| `CLOCK_GATING_EN` | boolean | false | Enable clock gating when CPU is in sleep mode (see sections <<_sleep_mode>> and <<_processor_clocking>>).
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| `INT_BOOTLOADER_EN` | boolean | false | Implement the processor-internal <<_bootloader_rom_bootrom>>, pre-initialized with the default <<_bootloader>> image.
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| `HART_ID` | suv(31:0) | 0x00000000 | The hart thread ID of the CPU (passed to <<_mhartid>> CSR).
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| `JEDEC_ID` | suv(10:0) | 00000000000 | JEDEC ID; continuation codes plus vendor ID (passed to <<_mvendorid>> CSR and to the <<_debug_transport_module_dtm>>).
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| `CLOCK_FREQUENCY` | natural | - | The clock frequency of the processor's `clk_i` input port in Hertz (Hz).
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| `CLOCK_GATING_EN` | boolean | false | Enable clock gating when CPU is in sleep mode (see sections <<_sleep_mode>> and <<_processor_clocking>>).
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| `INT_BOOTLOADER_EN` | boolean | false | Implement the processor-internal <<_bootloader_rom_bootrom>>, pre-initialized with the default <<_bootloader>> image.
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| `HART_ID` | suv(31:0) | 0x00000000 | The hart thread ID of the CPU (passed to <<_mhartid>> CSR).
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| `JEDEC_ID` | suv(10:0) | 0b00000000000 | JEDEC ID; continuation codes plus vendor ID (passed to <<_mvendorid>> CSR and to the <<_debug_transport_module_dtm>>).
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4+^| **<<_on_chip_debugger_ocd>>**
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| `ON_CHIP_DEBUGGER_EN` | boolean | false | Implement the on-chip debugger and the CPU debug mode.
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| `DM_LEGACY_MODE` | boolean | false | Debug module spec. version: `false` = v1.0, `true` = v0.13 (legacy mode).
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| `ON_CHIP_DEBUGGER_EN` | boolean | false | Implement the on-chip debugger and the CPU debug mode.
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| `DM_LEGACY_MODE` | boolean | false | Debug module spec. version: `false` = v1.0, `true` = v0.13 (legacy mode).
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4+^| **CPU <<_instruction_sets_and_extensions>>**
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| `RISCV_ISA_A` | boolean | false | Enable <<_a_isa_extension>> (atomic memory accesses).
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| `RISCV_ISA_B` | boolean | false | Enable <<_b_isa_extension>> (bit-manipulation).
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| `RISCV_ISA_C` | boolean | false | Enable <<_c_isa_extension>> (compressed instructions).
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| `RISCV_ISA_E` | boolean | false | Enable <<_e_isa_extension>> (reduced register file size).
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| `RISCV_ISA_M` | boolean | false | Enable <<_m_isa_extension>> (hardware-based integer multiplication and division).
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| `RISCV_ISA_U` | boolean | false | Enable <<_u_isa_extension>> (less-privileged user mode).
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| `RISCV_ISA_Zbkb` | boolean | false | Enable <<_zbkb_isa_extension>> (scalar cryptography bit manipulation instructions).
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| `RISCV_ISA_Zbkc` | boolean | false | Enable <<_zbkc_isa_extension>> (scalar cryptography carry-less multiplication instructions).
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| `RISCV_ISA_Zbkx` | boolean | false | Enable <<_zbkx_isa_extension>> (scalar cryptography crossbar permutations).
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| `RISCV_ISA_Zfinx` | boolean | false | Enable <<_zfinx_isa_extension>> (single-precision floating-point unit).
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| `RISCV_ISA_Zicntr` | boolean | true | Enable <<_zicntr_isa_extension>> (CPU base counters).
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| `RISCV_ISA_Zicond` | boolean | false | Enable <<_zicond_isa_extension>> (integer conditional instructions).
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| `RISCV_ISA_Zihpm` | boolean | false | Enable <<_zihpm_isa_extension>> (hardware performance monitors).
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| `RISCV_ISA_Zknd` | boolean | false | Enable <<_zknd_isa_extension>> (scalar cryptography NIST AES decryption instructions).
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| `RISCV_ISA_Zkne` | boolean | false | Enable <<_zkne_isa_extension>> (scalar cryptography NIST AES encryption instructions).
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| `RISCV_ISA_Zknh` | boolean | false | Enable <<_zknh_isa_extension>> (scalar cryptography NIST hash instructions).
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| `RISCV_ISA_Zksh` | boolean | false | Enable <<_zksh_isa_extension>> (scalar cryptography ShangMi hash functions).
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| `RISCV_ISA_Zksed` | boolean | false | Enable <<_zksed_isa_extension>> (scalar cryptography ShangMi block cyphers).
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| `RISCV_ISA_Zmmul` | boolean | false | Enable <<_zmmul_isa_extension>> (hardware-based integer multiplication).
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| `RISCV_ISA_Zxcfu` | boolean | false | Enable NEORV32-specific <<_zxcfu_isa_extension>> (custom RISC-V instructions).
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| `RISCV_ISA_A` | boolean | false | Enable <<_a_isa_extension>> (atomic memory accesses).
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| `RISCV_ISA_C` | boolean | false | Enable <<_c_isa_extension>> (compressed instructions).
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| `RISCV_ISA_E` | boolean | false | Enable <<_e_isa_extension>> (reduced register file size).
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| `RISCV_ISA_M` | boolean | false | Enable <<_m_isa_extension>> (hardware-based integer multiplication and division).
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| `RISCV_ISA_U` | boolean | false | Enable <<_u_isa_extension>> (less-privileged user mode).
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| `RISCV_ISA_Zba` | boolean | false | Enable <<_zba_isa_extension>> (shifted-add bit-manipulation instructions).
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| `RISCV_ISA_Zbb` | boolean | false | Enable <<_zbb_isa_extension>> (basic bit-manipulation instructions).
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| `RISCV_ISA_Zbkb` | boolean | false | Enable <<_zbkb_isa_extension>> (scalar cryptography bit manipulation instructions).
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| `RISCV_ISA_Zbkc` | boolean | false | Enable <<_zbkc_isa_extension>> (scalar cryptography carry-less multiplication instructions).
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| `RISCV_ISA_Zbkx` | boolean | false | Enable <<_zbkx_isa_extension>> (scalar cryptography crossbar permutations).
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| `RISCV_ISA_Zbs` | boolean | false | Enable <<_zbs_isa_extension>> (single-bit bit-manipulation instructions).
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| `RISCV_ISA_Zfinx` | boolean | false | Enable <<_zfinx_isa_extension>> (single-precision floating-point unit).
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| `RISCV_ISA_Zicntr` | boolean | true | Enable <<_zicntr_isa_extension>> (CPU base counters).
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| `RISCV_ISA_Zicond` | boolean | false | Enable <<_zicond_isa_extension>> (integer conditional instructions).
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| `RISCV_ISA_Zihpm` | boolean | false | Enable <<_zihpm_isa_extension>> (hardware performance monitors).
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| `RISCV_ISA_Zknd` | boolean | false | Enable <<_zknd_isa_extension>> (scalar cryptography NIST AES decryption instructions).
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| `RISCV_ISA_Zkne` | boolean | false | Enable <<_zkne_isa_extension>> (scalar cryptography NIST AES encryption instructions).
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| `RISCV_ISA_Zknh` | boolean | false | Enable <<_zknh_isa_extension>> (scalar cryptography NIST hash instructions).
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| `RISCV_ISA_Zksed` | boolean | false | Enable <<_zksed_isa_extension>> (scalar cryptography ShangMi block cyphers).
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| `RISCV_ISA_Zksh` | boolean | false | Enable <<_zksh_isa_extension>> (scalar cryptography ShangMi hash functions).
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| `RISCV_ISA_Zmmul` | boolean | false | Enable <<_zmmul_isa_extension>> (hardware-based integer multiplication).
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| `RISCV_ISA_Zxcfu` | boolean | false | Enable NEORV32-specific <<_zxcfu_isa_extension>> (custom RISC-V instructions).
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4+^| **CPU <<_architecture>> Tuning Options**
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| `FAST_MUL_EN` | boolean | false | Implement fast but large full-parallel multipliers (trying to infer DSP blocks); see section <<_cpu_arithmetic_logic_unit>>.
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| `FAST_SHIFT_EN` | boolean | false | Implement fast but large full-parallel barrel shifters; see section <<_cpu_arithmetic_logic_unit>>.
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| `REGFILE_HW_RST` | boolean | false | Implement full hardware reset for register file (use individual FFs instead of BRAM); see section <<_cpu_register_file>>.
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| `FAST_MUL_EN` | boolean | false | Implement fast but large full-parallel multipliers (trying to infer DSP blocks); see section <<_cpu_arithmetic_logic_unit>>.
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| `FAST_SHIFT_EN` | boolean | false | Implement fast but large full-parallel barrel shifters; see section <<_cpu_arithmetic_logic_unit>>.
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| `REGFILE_HW_RST` | boolean | false | Implement full hardware reset for register file (use individual FFs instead of BRAM); see section <<_cpu_register_file>>.
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4+^| **Physical Memory Protection (<<_smpmp_isa_extension>>)**
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| `PMP_NUM_REGIONS` | natural | 0 | Number of implemented PMP regions (0..16).
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| `PMP_MIN_GRANULARITY` | natural | 4 | Minimal region granularity in bytes. Has to be a power of two, min 4.
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| `PMP_TOR_MODE_EN` | boolean | true | Implement support for top-of-region (TOR) mode.
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| `PMP_NAP_MODE_EN` | boolean | true | Implement support for naturally-aligned power-of-two (NAPOT & NA4) modes.
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| `PMP_NUM_REGIONS` | natural | 0 | Number of implemented PMP regions (0..16).
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| `PMP_MIN_GRANULARITY` | natural | 4 | Minimal region granularity in bytes. Has to be a power of two, min 4.
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| `PMP_TOR_MODE_EN` | boolean | true | Implement support for top-of-region (TOR) mode.
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| `PMP_NAP_MODE_EN` | boolean | true | Implement support for naturally-aligned power-of-two (NAPOT & NA4) modes.
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4+^| **Hardware Performance Monitors (<<_zihpm_isa_extension>>)**
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| `HPM_NUM_CNTS` | natural | 0 | Number of implemented hardware performance monitor counters (0..13).
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| `HPM_CNT_WIDTH` | natural | 40 | Total LSB-aligned size of each HPM counter. Min 0, max 64.
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| `HPM_NUM_CNTS` | natural | 0 | Number of implemented hardware performance monitor counters (0..13).
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| `HPM_CNT_WIDTH` | natural | 40 | Total LSB-aligned size of each HPM counter. Min 0, max 64.
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4+^| **Internal <<_instruction_memory_imem>>**
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| `MEM_INT_IMEM_EN` | boolean | false | Implement the processor-internal instruction memory.
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| `MEM_INT_IMEM_SIZE` | natural | 16*1024 | Size in bytes of the processor internal instruction memory (use a power of 2).
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| `MEM_INT_IMEM_EN` | boolean | false | Implement the processor-internal instruction memory.
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| `MEM_INT_IMEM_SIZE` | natural | 16*1024 | Size in bytes of the processor internal instruction memory (use a power of 2).
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4+^| **Internal <<_data_memory_dmem>>**
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| `MEM_INT_DMEM_EN` | boolean | false | Implement the processor-internal data memory.
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| `MEM_INT_DMEM_SIZE` | natural | 8*1024 | Size in bytes of the processor-internal data memory (use a power of 2).
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| `MEM_INT_DMEM_EN` | boolean | false | Implement the processor-internal data memory.
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| `MEM_INT_DMEM_SIZE` | natural | 8*1024 | Size in bytes of the processor-internal data memory (use a power of 2).
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4+^| **<<_processor_internal_instruction_cache_icache>>**
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| `ICACHE_EN` | boolean | false | Implement the instruction cache.
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| `ICACHE_NUM_BLOCKS` | natural | 4 | Number of blocks ("lines") Has to be a power of two.
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| `ICACHE_BLOCK_SIZE` | natural | 64 | Size in bytes of each block. Has to be a power of two.
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| `ICACHE_EN` | boolean | false | Implement the instruction cache.
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| `ICACHE_NUM_BLOCKS` | natural | 4 | Number of blocks ("lines") Has to be a power of two.
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| `ICACHE_BLOCK_SIZE` | natural | 64 | Size in bytes of each block. Has to be a power of two.
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4+^| **<<_processor_internal_data_cache_dcache>>**
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| `DCACHE_EN` | boolean | false | Implement the data cache.
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| `DCACHE_NUM_BLOCKS` | natural | 4 | Number of blocks ("lines"). Has to be a power of two.
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| `DCACHE_BLOCK_SIZE` | natural | 64 | Size in bytes of each block. Has to be a power of two.
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| `DCACHE_EN` | boolean | false | Implement the data cache.
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| `DCACHE_NUM_BLOCKS` | natural | 4 | Number of blocks ("lines"). Has to be a power of two.
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| `DCACHE_BLOCK_SIZE` | natural | 64 | Size in bytes of each block. Has to be a power of two.
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4+^| **<<_processor_external_bus_interface_xbus>> (Wishbone b4 protocol)**
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| `XBUS_EN` | boolean | false | Implement the external bus interface.
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| `XBUS_TIMEOUT` | natural | 255 | Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception.
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| `XBUS_REGSTAGE_EN` | boolean | false | Implement XBUS register stages to ease timing closure.
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| `XBUS_CACHE_EN` | boolean | false | Implement the external bus cache.
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| `XBUS_CACHE_NUM_BLOCKS` | natural | 64 | Number of blocks ("lines"). Has to be a power of two.
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| `XBUS_CACHE_BLOCK_SIZE` | natural | 32 | Size in bytes of each block. Has to be a power of two.
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| `XBUS_EN` | boolean | false | Implement the external bus interface.
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| `XBUS_TIMEOUT` | natural | 255 | Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception.
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| `XBUS_REGSTAGE_EN` | boolean | false | Implement XBUS register stages to ease timing closure.
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| `XBUS_CACHE_EN` | boolean | false | Implement the external bus cache.
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| `XBUS_CACHE_NUM_BLOCKS` | natural | 64 | Number of blocks ("lines"). Has to be a power of two.
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| `XBUS_CACHE_BLOCK_SIZE` | natural | 32 | Size in bytes of each block. Has to be a power of two.
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4+^| **<<_execute_in_place_module_xip>>**
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| `XIP_EN` | boolean | false | Implement the execute in-place module.
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| `XIP_CACHE_EN` | boolean | false | Implement XIP cache.
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| `XIP_CACHE_NUM_BLOCKS` | natural | 8 | Number of blocks in XIP cache. Has to be a power of two.
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| `XIP_CACHE_BLOCK_SIZE` | natural | 256 | Number of bytes per XIP cache block. Has to be a power of two, min 4.
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| `XIP_EN` | boolean | false | Implement the execute in-place module.
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| `XIP_CACHE_EN` | boolean | false | Implement XIP cache.
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| `XIP_CACHE_NUM_BLOCKS` | natural | 8 | Number of blocks in XIP cache. Has to be a power of two.
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| `XIP_CACHE_BLOCK_SIZE` | natural | 256 | Number of bytes per XIP cache block. Has to be a power of two, min 4.
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4+^| **<<_external_interrupt_controller_xirq>>**
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| `XIRQ_NUM_CH` | natural | 0 | Number of channels of the external interrupt controller. Valid values are 0..32.
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| `XIRQ_NUM_CH` | natural | 0 | Number of channels of the external interrupt controller. Valid values are 0..32.
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4+^| **Peripheral/IO Modules**
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| `IO_DISABLE_SYSINFO` | boolean | false | Disable <<_system_configuration_information_memory_sysinfo>> module; ⚠️ not recommended - for advanced users only!
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| `IO_GPIO_NUM` | natural | 0 | Number of general purpose input/output pairs of the <<_general_purpose_input_and_output_port_gpio>>.
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| `IO_MTIME_EN` | boolean | false | Implement the <<_machine_system_timer_mtime>>.
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| `IO_UART0_EN` | boolean | false | Implement the <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>>.
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| `IO_UART0_RX_FIFO` | natural | 1 | UART0 RX FIFO depth, has to be a power of two, minimum value is 1, max 32768.
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| `IO_UART0_TX_FIFO` | natural | 1 | UART0 TX FIFO depth, has to be a power of two, minimum value is 1, max 32768.
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| `IO_UART1_EN` | boolean | false | Implement the <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>>.
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| `IO_UART1_RX_FIFO` | natural | 1 | UART1 RX FIFO depth, has to be a power of two, minimum value is 1, max 32768.
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| `IO_UART1_TX_FIFO` | natural | 1 | UART1 TX FIFO depth, has to be a power of two, minimum value is 1, max 32768.
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| `IO_SPI_EN` | boolean | false | Implement the <<_serial_peripheral_interface_controller_spi>>.
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| `IO_SPI_FIFO` | natural | 1 | Depth of the <<_serial_peripheral_interface_controller_spi>> FIFO. Has to be a power of two, min 1, max 32768.
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| `IO_SDI_EN` | boolean | false | Implement the <<_serial_data_interface_controller_sdi>>.
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| `IO_SDI_FIFO` | natural | 1 | Depth of the <<_serial_data_interface_controller_sdi>> FIFO. Has to be a power of two, min 1, max 32768.
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| `IO_TWI_EN` | boolean | false | Implement the <<_two_wire_serial_interface_controller_twi>>.
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| `IO_TWI_FIFO` | natural | 1 | Depth of the <<_two_wire_serial_interface_controller_twi>> FIFO. Has to be a power of two, min 1, max 32768.
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| `IO_PWM_NUM_CH` | natural | 0 | Number of channels of the <<_pulse_width_modulation_controller_pwm>> to implement (0..12).
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| `IO_WDT_EN` | boolean | false | Implement the <<_watchdog_timer_wdt>>.
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| `IO_TRNG_EN` | boolean | false | Implement the <<_true_random_number_generator_trng>>.
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| `IO_TRNG_FIFO` | natural | 1 | Depth of the TRNG data FIFO. Has to be a power of two, min 1, max 32768.
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| `IO_CFS_EN` | boolean | false | Implement the <<_custom_functions_subsystem_cfs>>.
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| `IO_CFS_CONFIG` | suv(31:0) | 0x00000000 | "Conduit" generic to pass user-defined flags to the <<_custom_functions_subsystem_cfs>>.
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| `IO_CFS_IN_SIZE` | natural | 32 | Size of the <<_custom_functions_subsystem_cfs>> input signal conduit (`cfs_in_i`).
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| `IO_CFS_OUT_SIZE` | natural | 32 | Size of the <<_custom_functions_subsystem_cfs>> output signal conduit (`cfs_out_o`).
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| `IO_NEOLED_EN` | boolean | false | Implement the <<_smart_led_interface_neoled>>.
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| `IO_NEOLED_TX_FIFO` | natural | 1 | TX FIFO depth of the the <<_smart_led_interface_neoled>>. Has to be a power of two, min 1, max 32768.
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| `IO_GPTMR_EN` | boolean | false | Implement the <<_general_purpose_timer_gptmr>>.
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| `IO_ONEWIRE_EN` | boolean | false | Implement the <<_one_wire_serial_interface_controller_onewire>>.
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| `IO_DMA_EN` | boolean | false | Implement the <<_direct_memory_access_controller_dma>>.
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| `IO_SLINK_EN` | boolean | false | Implement the <<_stream_link_interface_slink>>.
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| `IO_SLINK_RX_FIFO` | natural | 1 | SLINK RX FIFO depth, has to be a power of two, minimum value is 1, max 32768.
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| `IO_SLINK_TX_FIFO` | natural | 1 | SLINK TX FIFO depth, has to be a power of two, minimum value is 1, max 32768.
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| `IO_CRC_EN` | boolean | false | Implement the <<_cyclic_redundancy_check_crc>> unit.
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| `IO_DISABLE_SYSINFO` | boolean | false | Disable <<_system_configuration_information_memory_sysinfo>> module; ⚠️ not recommended - for advanced users only!
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| `IO_GPIO_NUM` | natural | 0 | Number of general purpose input/output pairs of the <<_general_purpose_input_and_output_port_gpio>>.
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| `IO_MTIME_EN` | boolean | false | Implement the <<_machine_system_timer_mtime>>.
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| `IO_UART0_EN` | boolean | false | Implement the <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>>.
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| `IO_UART0_RX_FIFO` | natural | 1 | UART0 RX FIFO depth, has to be a power of two, minimum value is 1, max 32768.
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| `IO_UART0_TX_FIFO` | natural | 1 | UART0 TX FIFO depth, has to be a power of two, minimum value is 1, max 32768.
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| `IO_UART1_EN` | boolean | false | Implement the <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>>.
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| `IO_UART1_RX_FIFO` | natural | 1 | UART1 RX FIFO depth, has to be a power of two, minimum value is 1, max 32768.
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| `IO_UART1_TX_FIFO` | natural | 1 | UART1 TX FIFO depth, has to be a power of two, minimum value is 1, max 32768.
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| `IO_SPI_EN` | boolean | false | Implement the <<_serial_peripheral_interface_controller_spi>>.
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| `IO_SPI_FIFO` | natural | 1 | Depth of the <<_serial_peripheral_interface_controller_spi>> FIFO. Has to be a power of two, min 1, max 32768.
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| `IO_SDI_EN` | boolean | false | Implement the <<_serial_data_interface_controller_sdi>>.
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| `IO_SDI_FIFO` | natural | 1 | Depth of the <<_serial_data_interface_controller_sdi>> FIFO. Has to be a power of two, min 1, max 32768.
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| `IO_TWI_EN` | boolean | false | Implement the <<_two_wire_serial_interface_controller_twi>>.
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| `IO_TWI_FIFO` | natural | 1 | Depth of the <<_two_wire_serial_interface_controller_twi>> FIFO. Has to be a power of two, min 1, max 32768.
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| `IO_PWM_NUM_CH` | natural | 0 | Number of channels of the <<_pulse_width_modulation_controller_pwm>> to implement (0..12).
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| `IO_WDT_EN` | boolean | false | Implement the <<_watchdog_timer_wdt>>.
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| `IO_TRNG_EN` | boolean | false | Implement the <<_true_random_number_generator_trng>>.
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| `IO_TRNG_FIFO` | natural | 1 | Depth of the TRNG data FIFO. Has to be a power of two, min 1, max 32768.
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| `IO_CFS_EN` | boolean | false | Implement the <<_custom_functions_subsystem_cfs>>.
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| `IO_CFS_CONFIG` | suv(31:0) | 0x00000000 | "Conduit" generic to pass user-defined flags to the <<_custom_functions_subsystem_cfs>>.
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| `IO_CFS_IN_SIZE` | natural | 32 | Size of the <<_custom_functions_subsystem_cfs>> input signal conduit (`cfs_in_i`).
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| `IO_CFS_OUT_SIZE` | natural | 32 | Size of the <<_custom_functions_subsystem_cfs>> output signal conduit (`cfs_out_o`).
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| `IO_NEOLED_EN` | boolean | false | Implement the <<_smart_led_interface_neoled>>.
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| `IO_NEOLED_TX_FIFO` | natural | 1 | TX FIFO depth of the the <<_smart_led_interface_neoled>>. Has to be a power of two, min 1, max 32768.
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| `IO_GPTMR_EN` | boolean | false | Implement the <<_general_purpose_timer_gptmr>>.
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||||
| `IO_ONEWIRE_EN` | boolean | false | Implement the <<_one_wire_serial_interface_controller_onewire>>.
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| `IO_DMA_EN` | boolean | false | Implement the <<_direct_memory_access_controller_dma>>.
|
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| `IO_SLINK_EN` | boolean | false | Implement the <<_stream_link_interface_slink>>.
|
||||
| `IO_SLINK_RX_FIFO` | natural | 1 | SLINK RX FIFO depth, has to be a power of two, minimum value is 1, max 32768.
|
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| `IO_SLINK_TX_FIFO` | natural | 1 | SLINK TX FIFO depth, has to be a power of two, minimum value is 1, max 32768.
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| `IO_CRC_EN` | boolean | false | Implement the <<_cyclic_redundancy_check_crc>> unit.
|
||||
|=======================
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ package neorv32_package is
|
|||
|
||||
-- Architecture Constants -----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100410"; -- hardware version
|
||||
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100411"; -- hardware version
|
||||
constant archid_c : natural := 19; -- official RISC-V architecture ID
|
||||
constant XLEN : natural := 32; -- native data path width
|
||||
|
||||
|
|
@ -677,14 +677,16 @@ package neorv32_package is
|
|||
DM_LEGACY_MODE : boolean := false;
|
||||
-- RISC-V CPU Extensions --
|
||||
RISCV_ISA_A : boolean := false;
|
||||
RISCV_ISA_B : boolean := false;
|
||||
RISCV_ISA_C : boolean := false;
|
||||
RISCV_ISA_E : boolean := false;
|
||||
RISCV_ISA_M : boolean := false;
|
||||
RISCV_ISA_U : boolean := false;
|
||||
RISCV_ISA_Zba : boolean := false;
|
||||
RISCV_ISA_Zbb : boolean := false;
|
||||
RISCV_ISA_Zbkb : boolean := false;
|
||||
RISCV_ISA_Zbkc : boolean := false;
|
||||
RISCV_ISA_Zbkx : boolean := false;
|
||||
RISCV_ISA_Zbs : boolean := false;
|
||||
RISCV_ISA_Zfinx : boolean := false;
|
||||
RISCV_ISA_Zicntr : boolean := true;
|
||||
RISCV_ISA_Zicond : boolean := false;
|
||||
|
|
|
|||
|
|
@ -33,26 +33,28 @@ entity neorv32_top is
|
|||
DM_LEGACY_MODE : boolean := false; -- debug module spec version: false = v1.0, true = v0.13
|
||||
|
||||
-- RISC-V CPU Extensions --
|
||||
RISCV_ISA_A : boolean := false; -- implement atomic memory operations extension?
|
||||
RISCV_ISA_B : boolean := false; -- implement bit-manipulation extension?
|
||||
RISCV_ISA_C : boolean := false; -- implement compressed extension?
|
||||
RISCV_ISA_E : boolean := false; -- implement embedded RF extension?
|
||||
RISCV_ISA_M : boolean := false; -- implement mul/div extension?
|
||||
RISCV_ISA_U : boolean := false; -- implement user mode extension?
|
||||
RISCV_ISA_Zbkb : boolean := false; -- implement bit-manipulation instructions for cryptography?
|
||||
RISCV_ISA_Zbkc : boolean := false; -- implement carry-less multiplication instructions?
|
||||
RISCV_ISA_Zbkx : boolean := false; -- implement cryptography crossbar permutation extension?
|
||||
RISCV_ISA_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)?
|
||||
RISCV_ISA_Zicntr : boolean := true; -- implement base counters?
|
||||
RISCV_ISA_Zicond : boolean := false; -- implement integer conditional operations?
|
||||
RISCV_ISA_Zihpm : boolean := false; -- implement hardware performance monitors?
|
||||
RISCV_ISA_Zknd : boolean := false; -- implement cryptography NIST AES decryption extension?
|
||||
RISCV_ISA_Zkne : boolean := false; -- implement cryptography NIST AES encryption extension?
|
||||
RISCV_ISA_Zknh : boolean := false; -- implement cryptography NIST hash extension?
|
||||
RISCV_ISA_Zksed : boolean := false; -- implement ShangMi block cypher extension?
|
||||
RISCV_ISA_Zksh : boolean := false; -- implement ShangMi hash extension?
|
||||
RISCV_ISA_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
|
||||
RISCV_ISA_Zxcfu : boolean := false; -- implement custom (instr.) functions unit?
|
||||
RISCV_ISA_A : boolean := false; -- implement atomic memory operations extension
|
||||
RISCV_ISA_C : boolean := false; -- implement compressed extension
|
||||
RISCV_ISA_E : boolean := false; -- implement embedded RF extension
|
||||
RISCV_ISA_M : boolean := false; -- implement mul/div extension
|
||||
RISCV_ISA_U : boolean := false; -- implement user mode extension
|
||||
RISCV_ISA_Zba : boolean := false; -- implement shifted-add bit-manipulation extension
|
||||
RISCV_ISA_Zbb : boolean := false; -- implement basic bit-manipulation extension
|
||||
RISCV_ISA_Zbkb : boolean := false; -- implement bit-manipulation instructions for cryptography
|
||||
RISCV_ISA_Zbkc : boolean := false; -- implement carry-less multiplication instructions
|
||||
RISCV_ISA_Zbkx : boolean := false; -- implement cryptography crossbar permutation extension
|
||||
RISCV_ISA_Zbs : boolean := false; -- implement single-bit bit-manipulation extension
|
||||
RISCV_ISA_Zfinx : boolean := false; -- implement 32-bit floating-point extension
|
||||
RISCV_ISA_Zicntr : boolean := true; -- implement base counters
|
||||
RISCV_ISA_Zicond : boolean := false; -- implement integer conditional operations
|
||||
RISCV_ISA_Zihpm : boolean := false; -- implement hardware performance monitors
|
||||
RISCV_ISA_Zknd : boolean := false; -- implement cryptography NIST AES decryption extension
|
||||
RISCV_ISA_Zkne : boolean := false; -- implement cryptography NIST AES encryption extension
|
||||
RISCV_ISA_Zknh : boolean := false; -- implement cryptography NIST hash extension
|
||||
RISCV_ISA_Zksed : boolean := false; -- implement ShangMi block cypher extension
|
||||
RISCV_ISA_Zksh : boolean := false; -- implement ShangMi hash extension
|
||||
RISCV_ISA_Zmmul : boolean := false; -- implement multiply-only M sub-extension
|
||||
RISCV_ISA_Zxcfu : boolean := false; -- implement custom (instr.) functions unit
|
||||
|
||||
-- Tuning Options --
|
||||
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
||||
|
|
@ -452,14 +454,16 @@ begin
|
|||
DEBUG_EXC_ADDR => dm_exc_entry_c,
|
||||
-- RISC-V ISA Extensions --
|
||||
RISCV_ISA_A => RISCV_ISA_A,
|
||||
RISCV_ISA_B => RISCV_ISA_B,
|
||||
RISCV_ISA_C => RISCV_ISA_C,
|
||||
RISCV_ISA_E => RISCV_ISA_E,
|
||||
RISCV_ISA_M => RISCV_ISA_M,
|
||||
RISCV_ISA_U => RISCV_ISA_U,
|
||||
RISCV_ISA_Zba => RISCV_ISA_Zba,
|
||||
RISCV_ISA_Zbb => RISCV_ISA_Zbb,
|
||||
RISCV_ISA_Zbkb => RISCV_ISA_Zbkb,
|
||||
RISCV_ISA_Zbkc => RISCV_ISA_Zbkc,
|
||||
RISCV_ISA_Zbkx => RISCV_ISA_Zbkx,
|
||||
RISCV_ISA_Zbs => RISCV_ISA_Zbs,
|
||||
RISCV_ISA_Zfinx => RISCV_ISA_Zfinx,
|
||||
RISCV_ISA_Zicntr => RISCV_ISA_Zicntr,
|
||||
RISCV_ISA_Zicond => RISCV_ISA_Zicond,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue