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[docs] update rv32i instruction timings

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stnolting 2025-04-05 17:28:42 +02:00
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docs/datasheet/cpu.adoc
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@ -639,17 +639,15 @@ The `I` ISA extensions is the base RISC-V integer ISA that is always enabled.
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| ALU | `add[i]` `slt[i]` `slt[i]u` `xor[i]` `or[i]` `and[i]` `sub` `lui` `auipc` | 2
| No-operation | "`nop`" | 2
| ALU shifts | `sll[i]` `srl[i]` `sra[i]` | 3 + 1..32; `CPU_FAST_SHIFT_EN`: 4
| Branches | `beq` `bne` `blt` `bge` `bltu` `bgeu` | taken: 6; not taken: 3
| Jump/call | `jal[r]` | 6
| Load/store | `lb` `lh` `lw` `lbu` `lhu` `sb` `sh` `sw` | 5
| System | `ecall` `ebreak` | 3
| Data fence | `fence` | depends on the memory system
| System | `wfi` | 3
| System | `mret` | 5
| Illegal inst. | - | 3
| ALU | `add[i]` `slt[i]` `slt[i]u` `xor[i]` `or[i]` `and[i]` `sub` `lui` `auipc` | 2
| ALU shifts | `sll[i]` `srl[i]` `sra[i]` | 3 + 1..32; `CPU_FAST_SHIFT_EN`: 4
| Branches | `beq` `bne` `blt` `bge` `bltu` `bgeu` | taken: 6; not taken: 3
| Jump/call | `jal[r]` | 6
| Load/store | `lb` `lh` `lw` `lbu` `lhu` `sb` `sh` `sw` | 5
| System | `ecall` `ebreak` | 3
| Data fence | `fence` | depends on the memory system
| System | `wfi` | 3
| System | `mret` | 6
|=======================
.`fence` Instruction