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[rtl] remove clock gating module

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stnolting 2025-03-21 19:47:41 +01:00
parent 40bccf4671
commit 96bee9ec3d
4 changed files with 0 additions and 56 deletions
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1
docs/datasheet/overview.adoc
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@ -179,7 +179,6 @@ rtl/core
├-neorv32_bus.vhd - SoC bus infrastructure modules
├-neorv32_cache.vhd - Generic cache module
├-neorv32_clint.vhd - Core local interruptor
├-neorv32_clockgate.vhd - Generic clock gating switch
├-neorv32_cfs.vhd - Custom functions subsystem
├-neorv32_cpu.vhd - NEORV32 CPU TOP ENTITY
├-neorv32_cpu_alu.vhd - Arithmetic/logic unit

53
rtl/core/neorv32_clockgate.vhd
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@ -1,53 +0,0 @@
-- ================================================================================ --
-- NEORV32 - Generic Clock Gating Switch --
-- -------------------------------------------------------------------------------- --
-- Especially for FPGA setups, it is highly recommended to replace this default --
-- module by a technology-/platform-specific macro or primitive (e.g. a dedicated --
-- clock mux) wrapper. --
-- -------------------------------------------------------------------------------- --
-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
-- Copyright (c) NEORV32 contributors. --
-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. --
-- Licensed under the BSD-3-Clause license, see LICENSE for details. --
-- SPDX-License-Identifier: BSD-3-Clause --
-- ================================================================================ --
library ieee;
use ieee.std_logic_1164.all;
entity neorv32_clockgate is
port (
clk_i : in std_ulogic; -- global clock line, always-on
rstn_i : in std_ulogic; -- global reset line, low-active, async
halt_i : in std_ulogic; -- shut down clock output when set
clk_o : out std_ulogic -- switched clock output
);
end neorv32_clockgate;
architecture neorv32_clockgate_rtl of neorv32_clockgate is
signal enable : std_ulogic;
begin
-- Warn about Clock Gating ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
assert false report "[NEORV32] Clock gating enabled (using default/generic clock switch)." severity warning;
-- Clock Switch ---------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
clock_switch: process(rstn_i, clk_i)
begin
if (rstn_i = '0') then
enable <= '1';
elsif falling_edge(clk_i) then -- update on falling edge to avoid glitches on 'clk_o'
enable <= not halt_i;
end if;
end process clock_switch;
-- for FPGA designs better replace this by a technology-specific primitive or macro --
clk_o <= clk_i when (enable = '1') else '0';
end neorv32_clockgate_rtl;

1
rtl/file_list_cpu.f
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@ -1,5 +1,4 @@
NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_package.vhd
NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_clockgate.vhd
NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_fifo.vhd
NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_cpu_decompressor.vhd
NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_cpu_frontend.vhd

1
rtl/file_list_soc.f
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@ -1,6 +1,5 @@
NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_package.vhd
NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_sys.vhd
NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_clockgate.vhd
NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_fifo.vhd
NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_cpu_decompressor.vhd
NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_cpu_frontend.vhd