[readme] add link to Vivado IP packaging

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stnolting 2024-05-08 17:57:41 +02:00
parent a6b0d6e4a4
commit a1c7709b3f

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@ -271,6 +271,7 @@ This overview provides some *quick links* to the most important sections of the
* [Simulation](https://stnolting.github.io/neorv32/ug/#_simulating_the_processor) - simulate the whole SoC
* [LiteX Integration](https://stnolting.github.io/neorv32/ug/#_litex_soc_builder_support) - build a SoC using NEORV32 + [LiteX](https://github.com/enjoy-digital/litex)
* [Convert to Verilog](https://stnolting.github.io/neorv32/ug/#_neorv32_in_verilog) - turn the NEORV32 into an all-Verilog design
* [Package as IP block](https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block) - turn the processor into an interactive AMD Vivado IP block
### :copyright: Legal