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🐛 fix atomic write/clear/set accesses of clear-only CSR bits (#829)
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stnolting
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commit
bf246fe020
9 changed files with 117 additions and 57 deletions
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@ -30,6 +30,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
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| Date | Version | Comment | Link |
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|:----:|:-------:|:--------|:----:|
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| 23.02.2024 | 1.9.5.9 | :bug: fix atomic write/clear/set accesses of clear-only CSR bits (re-fix of v1.9.5.6) | [#829](https://github.com/stnolting/neorv32/pull/829) |
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| 23.02.2024 | 1.9.5.8 | optimize FIFO component to improve technology mapping (inferring blockRAM for "async read" configuration); :bug: fix SLINK status flag delay | [#828](https://github.com/stnolting/neorv32/pull/828) |
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| 23.02.2024 | 1.9.5.7 | fix FIFO synthesis issue (Vivado cannot infer block RAM nor LUT-RAM) | [#827](https://github.com/stnolting/neorv32/pull/827) |
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| 20.02.2024 | 1.9.5.6 | :bug: fix bug in `mip.firq` CSR access; `mip.firq` bits are now read-write - software can trigger FIRQs by writing `1` to the according CSR bit | [#821](https://github.com/stnolting/neorv32/pull/821) |
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@ -892,6 +892,9 @@ As a custom extension, the NEORV32 CPU features 16 fast interrupt request (FIRQ)
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entity signals. These interrupts have custom configuration and status flags in the <<_mie>> and <<_mip>> CSRs and also
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provide custom trap codes in <<_mcause>>. These FIRQs are reserved for NEORV32 processor-internal usage only.
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Once triggered, the according FIRQ bits in <<_mip>> has to be cleared _manually_ by the FIRQ interrupt handler
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to clear/acknowledge the fast interrupt request.
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:sectnums:
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===== NEORV32 Trap Listing
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@ -443,7 +443,7 @@ However, any write-access will be ignored and will not cause an exception to mai
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| 3 | `CSR_MIP_MSIP` | r/- | **MSIP**: Machine _software_ interrupt pending; _cleared by platform-defined mechanism_
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| 7 | `CSR_MIP_MTIP` | r/- | **MTIP**: Machine _timer_ interrupt pending; _cleared by platform-defined mechanism_
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| 11 | `CSR_MIP_MEIP` | r/- | **MEIP**: Machine _external_ interrupt pending; _cleared by platform-defined mechanism_
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| 31:16 | `CSR_MIP_FIRQ15P` : `CSR_MIP_FIRQ0P` | r/w | **FIRQxP**: Fast interrupt channel 15..0 pending; has to be cleared manually by writing zero
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| 31:16 | `CSR_MIP_FIRQ15P` : `CSR_MIP_FIRQ0P` | r/c | **FIRQxP**: Fast interrupt channel 15..0 pending; has to be cleared manually by writing zero; writing `1` has no effect
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|=======================
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.FIRQ Channel Mapping
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@ -451,9 +451,6 @@ However, any write-access will be ignored and will not cause an exception to mai
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See section <<_neorv32_specific_fast_interrupt_requests>> for the mapping of the FIRQ channels and the according
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interrupt-triggering processor module.
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[NOTE]
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The FIRQ channels can be triggered manually by software by writing `1` to the according `mip` bit.
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{empty} +
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[discrete]
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@ -730,7 +730,7 @@ if it uses the trigger module for implementing a "hardware breakpoint"
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| 25 | `hit1` | r/- | `0` - hardwired to zero, only `hit0` is used
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| 24 | `vs` | r/- | `0` - VS-mode not supported
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| 23 | `vu` | r/- | `0` - VU-mode not supported
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| 22 | `hit0` | r/c | set when trigger has fired (**BEFORE** executing the triggering address); must be explicitly cleared by writing zero
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| 22 | `hit0` | r/c | set when trigger has fired (**BEFORE** executing the triggering address); must be explicitly cleared by writing zero; writing 1 has no effect
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| 21 | `select` | r/- | `0` - only address matching is supported
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| 20:19 | reserved | r/- | `00` - hardwired to zero
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| 18:16 | `size` | r/- | `000` - match accesses of any size
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@ -241,9 +241,11 @@ architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
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type csr_t is record
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addr : std_ulogic_vector(11 downto 0); -- csr address
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raddr : std_ulogic_vector(11 downto 0); -- simplified csr read address
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cmd : std_ulogic_vector(2 downto 0); -- CSR access command
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we, we_nxt : std_ulogic; -- csr write enable
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re, re_nxt : std_ulogic; -- csr read enable
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wdata, rdata : std_ulogic_vector(XLEN-1 downto 0); -- csr write/read data
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wmask : std_ulogic_vector(XLEN-1 downto 0); -- csr write data (mask)
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--
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mstatus_mie : std_ulogic; -- machine-mode IRQ enable
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mstatus_mpie : std_ulogic; -- previous machine-mode IRQ enable
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@ -255,7 +257,6 @@ architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
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mie_mei : std_ulogic; -- machine external interrupt enable
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mie_mti : std_ulogic; -- machine timer interrupt enable
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mie_firq : std_ulogic_vector(15 downto 0); -- fast interrupt enable
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mip_firq_wdata : std_ulogic_vector(15 downto 0); -- fast interrupt pending write data
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mip_firq_we : std_ulogic; -- fast interrupt pending write enable
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--
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privilege : std_ulogic; -- current privilege mode
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@ -279,7 +280,7 @@ architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
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dpc : std_ulogic_vector(XLEN-1 downto 0); -- mode program counter
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dscratch0 : std_ulogic_vector(XLEN-1 downto 0); -- debug mode scratch register 0
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--
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tdata1_hit_clr : std_ulogic; -- set to manually clear mcontrol6.hit0
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tdata1_hit_we : std_ulogic; -- mcontrol6.hit0 write access
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tdata1_execute : std_ulogic; -- enable instruction address match trigger
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tdata1_action : std_ulogic; -- enter debug mode / ebreak exception when trigger fires
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tdata1_dmode : std_ulogic; -- set to ignore tdata* CSR access from machine-mode
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@ -1453,10 +1454,10 @@ begin
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-- NEORV32-specific fast interrupts --
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for i in 0 to 15 loop
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if (csr.mip_firq_we = '1') then -- write access to MIP(.FIRQ) CSR
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trap_ctrl.irq_pnd(irq_firq_0_c+i) <= firq_i(i) or csr.mip_firq_wdata(i); -- keep buffering incoming FIRQs
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else
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trap_ctrl.irq_pnd(irq_firq_0_c+i) <= firq_i(i) or trap_ctrl.irq_pnd(irq_firq_0_c+i); -- keep pending FIRQs alive
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if (firq_i(i) = '1') then -- new incoming FIRQs have priority
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trap_ctrl.irq_pnd(irq_firq_0_c+i) <= '1';
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elsif (csr.mip_firq_we = '1') and (csr.wmask(16+i) = '0') then -- clear-only
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trap_ctrl.irq_pnd(irq_firq_0_c+i) <= '0';
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end if;
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end loop;
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@ -1592,23 +1593,32 @@ begin
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-- CSR Write Data -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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csr_write_data: process(execute_engine.ir, csr.rdata, rs1_i)
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variable tmp_v : std_ulogic_vector(XLEN-1 downto 0);
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csr.cmd <= execute_engine.ir(instr_funct3_msb_c downto instr_funct3_lsb_c); -- access type
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-- compute the write-data update mask --
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csr_write_mask: process(csr.cmd, execute_engine.ir, rs1_i)
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variable src_v : std_ulogic_vector(XLEN-1 downto 0);
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begin
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-- immediate/register operand --
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if (execute_engine.ir(instr_funct3_msb_c) = '1') then
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tmp_v := (others => '0');
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tmp_v(4 downto 0) := execute_engine.ir(19 downto 15); -- uimm5
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else
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tmp_v := rs1_i;
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-- CSR operand --
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if (csr.cmd(2) = '1') then -- immediate source
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src_v := (others => '0');
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src_v(4 downto 0) := execute_engine.ir(19 downto 15); -- uimm5
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else -- register source
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src_v := rs1_i;
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end if;
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-- tiny ALU to compute CSR write data --
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case execute_engine.ir(instr_funct3_msb_c-1 downto instr_funct3_lsb_c) is
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when "10" => csr.wdata <= csr.rdata or tmp_v; -- set
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when "11" => csr.wdata <= csr.rdata and (not tmp_v); -- clear
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when others => csr.wdata <= tmp_v; -- write
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end case;
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end process csr_write_data;
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-- actual write mask --
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if (csr.cmd(1 downto 0) = "11") then -- csrrc[i]: clear
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csr.wmask <= not src_v;
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else
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csr.wmask <= src_v;
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end if;
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end process csr_write_mask;
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-- tiny ALU to compute CSR write data --
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with csr.cmd(1 downto 0) select csr.wdata <=
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csr.rdata or csr.wmask when "10", -- csrrs[i]: set
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csr.rdata and csr.wmask when "11", -- csrrc[i]: clear
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csr.wmask when others; -- csrrw[i]: write
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-- External CSR Interface -----------------------------------------------------------------
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@ -1643,8 +1653,6 @@ begin
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csr.mtinst <= (others => '0');
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csr.mcounteren <= '0';
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csr.mcountinhibit <= (others => '0');
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csr.mip_firq_wdata <= (others => '0');
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csr.mip_firq_we <= '0';
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csr.dcsr_ebreakm <= '0';
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csr.dcsr_ebreaku <= '0';
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csr.dcsr_step <= '0';
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@ -1652,17 +1660,14 @@ begin
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csr.dcsr_cause <= (others => '0');
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csr.dpc <= CPU_BOOT_ADDR(XLEN-1 downto 2) & "00"; -- 32-bit aligned boot address
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csr.dscratch0 <= (others => '0');
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csr.tdata1_hit_clr <= '0';
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csr.tdata1_execute <= '0';
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csr.tdata1_action <= '0';
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csr.tdata1_dmode <= '0';
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csr.tdata2 <= (others => '0');
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elsif rising_edge(clk_i) then
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-- defaults --
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csr.we <= csr.we_nxt and (not trap_ctrl.exc_buf(exc_illegal_c)); -- write if not an illegal instruction
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csr.mip_firq_we <= '0'; -- no write to MIP.FIRQ by default
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csr.tdata1_hit_clr <= '0';
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-- write if not an illegal instruction --
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csr.we <= csr.we_nxt and (not trap_ctrl.exc_buf(exc_illegal_c));
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-- ********************************************************************************
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-- CSR access by application software
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@ -1721,9 +1726,8 @@ begin
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when csr_mcause_c => -- machine trap cause
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csr.mcause <= csr.wdata(31) & csr.wdata(4 downto 0); -- type (exception/interrupt) & identifier
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when csr_mip_c => -- machine interrupt pending
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csr.mip_firq_wdata <= csr.wdata(31 downto 16);
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csr.mip_firq_we <= '1'; -- trigger MIP.FIRQ write
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-- when csr_mip_c => -- machine interrupt pending
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-- only the FIRQs are writable (clear-only); the actual mip.firq write logic is in <interrupt_buffer>
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-- --------------------------------------------------------------------
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-- machine counter setup --
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@ -1771,7 +1775,6 @@ begin
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if (csr.tdata1_dmode = '0') or (debug_ctrl.running = '1') then -- write access from debug-mode only?
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csr.tdata1_execute <= csr.wdata(2);
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csr.tdata1_action <= csr.wdata(12);
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csr.tdata1_hit_clr <= not csr.wdata(22);
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end if;
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if (debug_ctrl.running = '1') then -- writable from debug-mode only
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csr.tdata1_dmode <= csr.wdata(27);
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@ -1917,6 +1920,10 @@ begin
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end if;
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end process csr_write_access;
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-- out-of-process CSR write access --
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csr.mip_firq_we <= '1' when (csr.we = '1') and (csr.cmd(0) = '1') and (csr.addr = csr_mip_c) else '0'; -- mip.firq: write/clear only
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csr.tdata1_hit_we <= '1' when (csr.we = '1') and (csr.cmd(0) = '1') and (csr.addr = csr_tdata1_c) else '0'; -- tdata1.hit: write/clear only
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-- effective privilege mode is MACHINE when in debug mode --
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csr.privilege_eff <= priv_mode_m_c when (debug_ctrl.running = '1') else csr.privilege;
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@ -2413,7 +2420,7 @@ begin
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elsif rising_edge(clk_i) then
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if (hw_trigger_match = '1') and (trap_ctrl.exc_buf(exc_ebreak_c) = '1') then -- trigger has fired and breakpoint exception is pending
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hw_trigger_fired <= '1';
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elsif (csr.tdata1_hit_clr = '1') then
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elsif (csr.tdata1_hit_we = '1') and (csr.wmask(22) = '0') then -- clear-only
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hw_trigger_fired <= '0';
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end if;
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end if;
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@ -53,7 +53,7 @@ package neorv32_package is
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090508"; -- hardware version
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090509"; -- hardware version
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constant archid_c : natural := 19; -- official RISC-V architecture ID
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constant XLEN : natural := 32; -- native data path width
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@ -185,7 +185,7 @@ begin
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if ci_mode then
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-- No need to send the full expectation in one big chunk
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check_uart(net, uart1_rx_handle, nul & nul);
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check_uart(net, uart1_rx_handle, "0/57" & cr & lf);
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check_uart(net, uart1_rx_handle, "0/58" & cr & lf);
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end if;
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-- Wait until all expected data has been received
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@ -514,7 +514,7 @@ int main() {
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// No "real" CSR write access (because rs1 = r0)
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, mcause_never_c);
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PRINT_STANDARD("[%i] Read-only CSR 'no-write' ", cnt_test);
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PRINT_STANDARD("[%i] Read-only CSR (no-write) ", cnt_test);
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cnt_test++;
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@ -530,6 +530,58 @@ int main() {
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}
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// ----------------------------------------------------------
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// Test MIP.FIRQ clear-only bits
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, mcause_never_c);
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PRINT_STANDARD("[%i] Clear-only CSR (mip.FIRQ) ", cnt_test);
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if ((NEORV32_SYSINFO->SOC & (1 << SYSINFO_SOC_IO_SPI)) && (NEORV32_SYSINFO->SOC & (1 << SYSINFO_SOC_IO_GPTMR))) {
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cnt_test++;
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tmp_a = 0; // error counter
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// disable all IRQ sources
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neorv32_cpu_csr_write(CSR_MIE, 0);
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// trigger two FIRQs
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neorv32_gptmr_setup(CLK_PRSC_2, 1, -1); // fire GPTMR FIRQ
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neorv32_spi_setup(CLK_PRSC_2, 0, 0, 0, -1); // fire SPI FIRQ
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neorv32_gptmr_disable();
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neorv32_spi_disable();
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// both FIRQs should be pending now
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if ((neorv32_cpu_csr_read(CSR_MIP) & 0xffff0000) != ((1 << SPI_FIRQ_PENDING) + (1 << GPTMR_FIRQ_PENDING))) {
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tmp_a++;
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}
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// test write/set/clear access
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neorv32_cpu_csr_write(CSR_MIP, 0xffffffff); // should have no effect at all
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neorv32_cpu_csr_set(CSR_MIP, 0xffffffff); // should have no effect at all
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neorv32_cpu_csr_clr(CSR_MIP, 1 << SPI_FIRQ_PENDING); // clear SPI FIRQ only
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if ((neorv32_cpu_csr_read(CSR_MIP) & 0xffff0000) != (1 << GPTMR_FIRQ_PENDING)) {
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tmp_a++;
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}
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// clear all mip.FIRQ bits
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neorv32_cpu_csr_write(CSR_MIP, 0);
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if ((neorv32_cpu_csr_read(CSR_MIP) & 0xffff0000) != 0) {
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tmp_a++;
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}
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if (tmp_a == 0) {
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test_ok();
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}
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else {
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test_fail();
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}
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}
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else {
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PRINT_STANDARD("[n.a.]\n");
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}
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// ----------------------------------------------------------
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// Unaligned instruction address
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// ----------------------------------------------------------
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@ -304,22 +304,22 @@ enum NEORV32_CSR_MIP_enum {
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CSR_MIP_MEIP = 11, /**< CPU mip CSR (11): MEIP - Machine external interrupt pending (r/-) */
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/* NEORV32-specific extension: Fast Interrupt Requests (FIRQ) */
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CSR_MIP_FIRQ0P = 16, /**< CPU mip CSR (16): FIRQ0P - Fast interrupt channel 0 pending (r/w) */
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CSR_MIP_FIRQ1P = 17, /**< CPU mip CSR (17): FIRQ1P - Fast interrupt channel 1 pending (r/w) */
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CSR_MIP_FIRQ2P = 18, /**< CPU mip CSR (18): FIRQ2P - Fast interrupt channel 2 pending (r/w) */
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CSR_MIP_FIRQ3P = 19, /**< CPU mip CSR (19): FIRQ3P - Fast interrupt channel 3 pending (r/w) */
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CSR_MIP_FIRQ4P = 20, /**< CPU mip CSR (20): FIRQ4P - Fast interrupt channel 4 pending (r/w) */
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CSR_MIP_FIRQ5P = 21, /**< CPU mip CSR (21): FIRQ5P - Fast interrupt channel 5 pending (r/w) */
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CSR_MIP_FIRQ6P = 22, /**< CPU mip CSR (22): FIRQ6P - Fast interrupt channel 6 pending (r/w) */
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CSR_MIP_FIRQ7P = 23, /**< CPU mip CSR (23): FIRQ7P - Fast interrupt channel 7 pending (r/w) */
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CSR_MIP_FIRQ8P = 24, /**< CPU mip CSR (24): FIRQ8P - Fast interrupt channel 8 pending (r/w) */
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CSR_MIP_FIRQ9P = 25, /**< CPU mip CSR (25): FIRQ9P - Fast interrupt channel 9 pending (r/w) */
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CSR_MIP_FIRQ10P = 26, /**< CPU mip CSR (26): FIRQ10P - Fast interrupt channel 10 pending (r/w) */
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CSR_MIP_FIRQ11P = 27, /**< CPU mip CSR (27): FIRQ11P - Fast interrupt channel 11 pending (r/w) */
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CSR_MIP_FIRQ12P = 28, /**< CPU mip CSR (28): FIRQ12P - Fast interrupt channel 12 pending (r/w) */
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CSR_MIP_FIRQ13P = 29, /**< CPU mip CSR (29): FIRQ13P - Fast interrupt channel 13 pending (r/w) */
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CSR_MIP_FIRQ14P = 30, /**< CPU mip CSR (30): FIRQ14P - Fast interrupt channel 14 pending (r/w) */
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CSR_MIP_FIRQ15P = 31 /**< CPU mip CSR (31): FIRQ15P - Fast interrupt channel 15 pending (r/w) */
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CSR_MIP_FIRQ0P = 16, /**< CPU mip CSR (16): FIRQ0P - Fast interrupt channel 0 pending (r/c) */
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CSR_MIP_FIRQ1P = 17, /**< CPU mip CSR (17): FIRQ1P - Fast interrupt channel 1 pending (r/c) */
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CSR_MIP_FIRQ2P = 18, /**< CPU mip CSR (18): FIRQ2P - Fast interrupt channel 2 pending (r/c) */
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CSR_MIP_FIRQ3P = 19, /**< CPU mip CSR (19): FIRQ3P - Fast interrupt channel 3 pending (r/c) */
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CSR_MIP_FIRQ4P = 20, /**< CPU mip CSR (20): FIRQ4P - Fast interrupt channel 4 pending (r/c) */
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CSR_MIP_FIRQ5P = 21, /**< CPU mip CSR (21): FIRQ5P - Fast interrupt channel 5 pending (r/c) */
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CSR_MIP_FIRQ6P = 22, /**< CPU mip CSR (22): FIRQ6P - Fast interrupt channel 6 pending (r/c) */
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CSR_MIP_FIRQ7P = 23, /**< CPU mip CSR (23): FIRQ7P - Fast interrupt channel 7 pending (r/c) */
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CSR_MIP_FIRQ8P = 24, /**< CPU mip CSR (24): FIRQ8P - Fast interrupt channel 8 pending (r/c) */
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CSR_MIP_FIRQ9P = 25, /**< CPU mip CSR (25): FIRQ9P - Fast interrupt channel 9 pending (r/c) */
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CSR_MIP_FIRQ10P = 26, /**< CPU mip CSR (26): FIRQ10P - Fast interrupt channel 10 pending (r/c) */
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CSR_MIP_FIRQ11P = 27, /**< CPU mip CSR (27): FIRQ11P - Fast interrupt channel 11 pending (r/c) */
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CSR_MIP_FIRQ12P = 28, /**< CPU mip CSR (28): FIRQ12P - Fast interrupt channel 12 pending (r/c) */
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CSR_MIP_FIRQ13P = 29, /**< CPU mip CSR (29): FIRQ13P - Fast interrupt channel 13 pending (r/c) */
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CSR_MIP_FIRQ14P = 30, /**< CPU mip CSR (30): FIRQ14P - Fast interrupt channel 14 pending (r/c) */
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CSR_MIP_FIRQ15P = 31 /**< CPU mip CSR (31): FIRQ15P - Fast interrupt channel 15 pending (r/c) */
|
||||
};
|
||||
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||||
|
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|
|
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Loading…
Add table
Add a link
Reference in a new issue