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https://github.com/stnolting/neorv32.git
synced 2025-04-24 06:07:52 -04:00
[rtl] cpu: remove clock gating option
This commit is contained in:
stnolting
parent
96bee9ec3d
commit
f33db178ce
1 changed files with 62 additions and 86 deletions
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@ -55,7 +55,6 @@ entity neorv32_cpu is
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RISCV_ISA_Sdtrig : boolean; -- implement trigger module extension
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RISCV_ISA_Smpmp : boolean; -- implement physical memory protection
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-- Tuning Options --
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CPU_CLOCK_GATING_EN : boolean; -- enable clock gating when in sleep mode
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CPU_FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
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CPU_FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
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CPU_RF_HW_RST_EN : boolean; -- implement full hardware reset for register file
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@ -109,7 +108,6 @@ architecture neorv32_cpu_rtl of neorv32_cpu is
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-- local signals --
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signal ctrl : ctrl_bus_t; -- main control bus
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signal clk_gated : std_ulogic; -- switchable clock (clock gating)
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signal frontend : if_bus_t; -- instruction-fetch interface
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signal rf_wdata : std_ulogic_vector(XLEN-1 downto 0); -- register file write data
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signal rs1 : std_ulogic_vector(XLEN-1 downto 0); -- source register 1
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@ -174,10 +172,9 @@ begin
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-- CPU tuning options --
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assert false report "[NEORV32] CPU tuning options: " &
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cond_sel_string_f(CPU_CLOCK_GATING_EN, "clock_gating ", "") &
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cond_sel_string_f(CPU_FAST_MUL_EN, "fast_mul ", "") &
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cond_sel_string_f(CPU_FAST_SHIFT_EN, "fast_shift ", "") &
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cond_sel_string_f(CPU_RF_HW_RST_EN, "rf_hw_rst ", "")
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cond_sel_string_f(CPU_FAST_MUL_EN, "fast_mul ", "") &
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cond_sel_string_f(CPU_FAST_SHIFT_EN, "fast_shift ", "") &
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cond_sel_string_f(CPU_RF_HW_RST_EN, "rf_hw_rst ", "")
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severity note;
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-- simulation notifier --
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@ -186,25 +183,6 @@ begin
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end generate; -- /hello_neorv32
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-- Clock Gating ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_clockgate_enabled:
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if CPU_CLOCK_GATING_EN generate
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neorv32_cpu_clockgate_inst: entity neorv32.neorv32_clockgate
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port map (
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clk_i => clk_i,
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rstn_i => rstn_i,
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halt_i => ctrl.cpu_sleep,
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clk_o => clk_gated
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);
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end generate;
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neorv32_cpu_clockgate_disabled:
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if not CPU_CLOCK_GATING_EN generate
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clk_gated <= clk_i;
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end generate;
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-- Front-End (Instruction Fetch) ----------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_frontend_inst: entity neorv32.neorv32_cpu_frontend
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@ -213,7 +191,7 @@ begin
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)
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port map (
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-- global control --
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clk_i => clk_gated, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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-- instruction fetch interface --
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@ -229,52 +207,50 @@ begin
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neorv32_cpu_control_inst: entity neorv32.neorv32_cpu_control
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generic map (
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-- General --
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HART_ID => HART_ID, -- hardware thread ID
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BOOT_ADDR => BOOT_ADDR, -- cpu boot address
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DEBUG_PARK_ADDR => DEBUG_PARK_ADDR, -- cpu debug mode parking loop entry address
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DEBUG_EXC_ADDR => DEBUG_EXC_ADDR, -- cpu debug mode exception entry address
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HART_ID => HART_ID, -- hardware thread ID
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BOOT_ADDR => BOOT_ADDR, -- cpu boot address
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DEBUG_PARK_ADDR => DEBUG_PARK_ADDR, -- cpu debug mode parking loop entry address
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DEBUG_EXC_ADDR => DEBUG_EXC_ADDR, -- cpu debug mode exception entry address
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-- RISC-V ISA Extensions --
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RISCV_ISA_A => riscv_a_c, -- implement atomic memory operations extension
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RISCV_ISA_B => riscv_b_c, -- implement bit-manipulation extension
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RISCV_ISA_C => RISCV_ISA_C, -- implement compressed extension
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RISCV_ISA_E => RISCV_ISA_E, -- implement embedded RF extension
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RISCV_ISA_M => RISCV_ISA_M, -- implement mul/div extension
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RISCV_ISA_U => RISCV_ISA_U, -- implement user mode extension
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RISCV_ISA_Zaamo => RISCV_ISA_Zaamo, -- implement atomic read-modify-write operations extension
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RISCV_ISA_Zalrsc => RISCV_ISA_Zalrsc, -- implement atomic reservation-set operations extension
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RISCV_ISA_Zba => RISCV_ISA_Zba, -- implement shifted-add bit-manipulation extension
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RISCV_ISA_Zbb => RISCV_ISA_Zbb, -- implement basic bit-manipulation extension
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RISCV_ISA_Zbkb => RISCV_ISA_Zbkb, -- implement bit-manipulation instructions for cryptography
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RISCV_ISA_Zbkc => RISCV_ISA_Zbkc, -- implement carry-less multiplication instructions
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RISCV_ISA_Zbkx => RISCV_ISA_Zbkx, -- implement cryptography crossbar permutation extension
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RISCV_ISA_Zbs => RISCV_ISA_Zbs, -- implement single-bit bit-manipulation extension
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RISCV_ISA_Zfinx => RISCV_ISA_Zfinx, -- implement 32-bit floating-point extension
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RISCV_ISA_Zicntr => RISCV_ISA_Zicntr, -- implement base counters
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RISCV_ISA_Zicond => RISCV_ISA_Zicond, -- implement integer conditional operations
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RISCV_ISA_Zihpm => RISCV_ISA_Zihpm, -- implement hardware performance monitors
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RISCV_ISA_Zkn => riscv_zkn_c, -- NIST algorithm suite available
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RISCV_ISA_Zknd => RISCV_ISA_Zknd, -- implement cryptography NIST AES decryption extension
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RISCV_ISA_Zkne => RISCV_ISA_Zkne, -- implement cryptography NIST AES encryption extension
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RISCV_ISA_Zknh => RISCV_ISA_Zknh, -- implement cryptography NIST hash extension
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RISCV_ISA_Zks => riscv_zks_c, -- ShangMi algorithm suite available
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RISCV_ISA_Zksed => RISCV_ISA_Zksed, -- implement ShangMi block cipher extension
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RISCV_ISA_Zksh => RISCV_ISA_Zksh, -- implement ShangMi hash extension
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RISCV_ISA_Zkt => riscv_zkt_c, -- data-independent execution time available (for cryptographic operations)
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RISCV_ISA_Zmmul => RISCV_ISA_Zmmul, -- implement multiply-only M sub-extension
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RISCV_ISA_Zxcfu => RISCV_ISA_Zxcfu, -- implement custom (instr.) functions unit
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RISCV_ISA_Sdext => RISCV_ISA_Sdext, -- implement external debug mode extension
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RISCV_ISA_Sdtrig => RISCV_ISA_Sdtrig, -- implement trigger module extension
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RISCV_ISA_Smpmp => RISCV_ISA_Smpmp, -- implement physical memory protection
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RISCV_ISA_A => riscv_a_c, -- implement atomic memory operations extension
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RISCV_ISA_B => riscv_b_c, -- implement bit-manipulation extension
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RISCV_ISA_C => RISCV_ISA_C, -- implement compressed extension
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RISCV_ISA_E => RISCV_ISA_E, -- implement embedded RF extension
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RISCV_ISA_M => RISCV_ISA_M, -- implement mul/div extension
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RISCV_ISA_U => RISCV_ISA_U, -- implement user mode extension
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RISCV_ISA_Zaamo => RISCV_ISA_Zaamo, -- implement atomic read-modify-write operations extension
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RISCV_ISA_Zalrsc => RISCV_ISA_Zalrsc, -- implement atomic reservation-set operations extension
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RISCV_ISA_Zba => RISCV_ISA_Zba, -- implement shifted-add bit-manipulation extension
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RISCV_ISA_Zbb => RISCV_ISA_Zbb, -- implement basic bit-manipulation extension
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RISCV_ISA_Zbkb => RISCV_ISA_Zbkb, -- implement bit-manipulation instructions for cryptography
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RISCV_ISA_Zbkc => RISCV_ISA_Zbkc, -- implement carry-less multiplication instructions
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RISCV_ISA_Zbkx => RISCV_ISA_Zbkx, -- implement cryptography crossbar permutation extension
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RISCV_ISA_Zbs => RISCV_ISA_Zbs, -- implement single-bit bit-manipulation extension
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RISCV_ISA_Zfinx => RISCV_ISA_Zfinx, -- implement 32-bit floating-point extension
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RISCV_ISA_Zicntr => RISCV_ISA_Zicntr, -- implement base counters
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RISCV_ISA_Zicond => RISCV_ISA_Zicond, -- implement integer conditional operations
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RISCV_ISA_Zihpm => RISCV_ISA_Zihpm, -- implement hardware performance monitors
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RISCV_ISA_Zkn => riscv_zkn_c, -- NIST algorithm suite available
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RISCV_ISA_Zknd => RISCV_ISA_Zknd, -- implement cryptography NIST AES decryption extension
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RISCV_ISA_Zkne => RISCV_ISA_Zkne, -- implement cryptography NIST AES encryption extension
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RISCV_ISA_Zknh => RISCV_ISA_Zknh, -- implement cryptography NIST hash extension
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RISCV_ISA_Zks => riscv_zks_c, -- ShangMi algorithm suite available
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RISCV_ISA_Zksed => RISCV_ISA_Zksed, -- implement ShangMi block cipher extension
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RISCV_ISA_Zksh => RISCV_ISA_Zksh, -- implement ShangMi hash extension
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RISCV_ISA_Zkt => riscv_zkt_c, -- data-independent execution time available (for cryptographic operations)
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RISCV_ISA_Zmmul => RISCV_ISA_Zmmul, -- implement multiply-only M sub-extension
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RISCV_ISA_Zxcfu => RISCV_ISA_Zxcfu, -- implement custom (instr.) functions unit
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RISCV_ISA_Sdext => RISCV_ISA_Sdext, -- implement external debug mode extension
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RISCV_ISA_Sdtrig => RISCV_ISA_Sdtrig, -- implement trigger module extension
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RISCV_ISA_Smpmp => RISCV_ISA_Smpmp, -- implement physical memory protection
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-- Tuning Options --
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CPU_CLOCK_GATING_EN => CPU_CLOCK_GATING_EN, -- enable clock gating when in sleep mode
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CPU_FAST_MUL_EN => CPU_FAST_MUL_EN, -- use DSPs for M extension's multiplier
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CPU_FAST_SHIFT_EN => CPU_FAST_SHIFT_EN, -- use barrel shifter for shift operations
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CPU_RF_HW_RST_EN => CPU_RF_HW_RST_EN -- implement full hardware reset for register file
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CPU_FAST_MUL_EN => CPU_FAST_MUL_EN, -- use DSPs for M extension's multiplier
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CPU_FAST_SHIFT_EN => CPU_FAST_SHIFT_EN, -- use barrel shifter for shift operations
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CPU_RF_HW_RST_EN => CPU_RF_HW_RST_EN -- implement full hardware reset for register file
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)
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port map (
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-- global control --
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clk_i => clk_gated, -- global clock, rising edge
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clk_aux_i => clk_i, -- always-on clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_o => ctrl, -- main control bus
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-- instruction fetch (front-end) interface --
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@ -320,11 +296,11 @@ begin
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)
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port map (
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-- global control --
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clk_i => clk_gated, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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-- read back --
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rdata_o => xcsr_cnt -- read data
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rdata_o => xcsr_cnt -- read data
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);
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end generate;
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@ -344,14 +320,14 @@ begin
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)
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port map (
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-- global control --
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clk_i => clk_gated, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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-- operands --
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rd_i => rf_wdata, -- destination operand rd
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rs1_o => rs1, -- source operand rs1
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rs2_o => rs2, -- source operand rs2
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rs3_o => rs3 -- source operand rs3
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rd_i => rf_wdata, -- destination operand rd
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rs1_o => rs1, -- source operand rs1
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rs2_o => rs2, -- source operand rs2
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rs3_o => rs3 -- source operand rs3
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);
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-- all buses are zero unless there is an according operation --
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@ -385,7 +361,7 @@ begin
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)
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port map (
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-- global control --
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clk_i => clk_gated, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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-- data input --
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@ -407,7 +383,7 @@ begin
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neorv32_cpu_lsu_inst: entity neorv32.neorv32_cpu_lsu
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port map (
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-- global control --
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clk_i => clk_gated, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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-- cpu data access interface --
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@ -437,15 +413,15 @@ begin
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)
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port map (
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-- global control --
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clk_i => clk_gated, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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-- CSR interface --
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csr_o => xcsr_pmp, -- read data
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csr_o => xcsr_pmp, -- read data
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-- address input --
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addr_ls_i => alu_add, -- load/store address
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addr_ls_i => alu_add, -- load/store address
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-- access error --
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fault_o => pmp_fault -- permission violation
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fault_o => pmp_fault -- permission violation
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);
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end generate;
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