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Signed-off-by: stnolting <stnolting@gmail.com>
309 lines
26 KiB
Markdown
309 lines
26 KiB
Markdown
[](https://github.com/stnolting/neorv32)
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# The NEORV32 RISC-V Processor
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[](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[](https://stnolting.github.io/neorv32)
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[](https://github.com/stnolting/neorv32/releases/tag/nightly)
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[](https://stnolting.github.io/neorv32/ug)
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[](https://stnolting.github.io/neorv32/sw/files.html)
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1. [Overview](#1-overview)
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* [Key Features](#key-features)
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* [Project Status](#project-status)
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2. [Features](#2-features)
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3. [FPGA Implementation Results](#3-fpga-implementation-results)
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4. [Performance](#4-performance)
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5. [**Getting Started**](#5-getting-started) :rocket:
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## 1. Overview
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The NEORV32 Processor is a **customizable microcontroller-like system on chip (SoC)** built around the NEORV32
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[RISC-V](https://riscv.org/) CPU that is written in **platform-independent VHDL**. The processor is intended as auxiliary
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controller in larger SoC designs or as tiny and customized microcontroller that even fits into a
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Lattice iCE40 UltraPlus low-power & low-density FPGA. The project is intended to work _out of the box_ and targets
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FPGA / RISC-V beginners as well as advanced users.
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Special focus is paid on **execution safety** to provide defined and predictable behavior at any time.
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For example, the CPU ensures _all_ memory accesses are properly acknowledged and _all_ invalid/malformed
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instructions are always detected as such. Whenever an unexpected state occurs the application software is
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informed via _precise_ and resumable hardware exceptions.
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* :recycle: Looking for an **all-Verilog** version? Have a look at [neorv32-verilog](https://github.com/stnolting/neorv32-verilog).
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* :heavy_check_mark: [Continuous integration](#project-status) to check for regressions (including RISC-V ISA compatibility check using **RISCOF**).
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* :open_file_folder: [Exemplary setups](https://github.com/stnolting/neorv32-setups) and
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[community projects](https://github.com/stnolting/neorv32-setups/blob/main/README.md#Community-Projects)
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targeting various FPGA boards and toolchains to get started.
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* :package: The entire processor is also available as [Vivado IP Block](https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block).
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* :kite: Support for [FreeRTOS](https://github.com/stnolting/neorv32-freertos),
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[Zephyr OS](https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html) and
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[LiteX](https://github.com/enjoy-digital/litex/wiki/CPUs#risc-v---neorv32) SoC Builder Framework.
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* :desktop_computer: Pre-configured [Eclipse project](https://stnolting.github.io/neorv32/ug/#_eclipse_ide) for developing and debugging code using an IDE.
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* :label: The project's change log is available in [CHANGELOG.md](https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md).
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* :rocket: Check out the [quick links below](#5-getting-started) and the
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[*User Guide*](https://stnolting.github.io/neorv32/ug/) to get started setting up _your_ NEORV32 processor!
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* :books: For detailed information see the [NEORV32 online documentation](https://stnolting.github.io/neorv32/).
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* :interrobang: Want to know more? Check out the [project's rationale](https://stnolting.github.io/neorv32/#_rationale).
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Feel free to open a new [issue](https://github.com/stnolting/neorv32/issues) or start a new
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[discussion](https://github.com/stnolting/neorv32/discussions) if you have questions, comments, ideas, feedback or if something is
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not working as expected. See how to [contribute](https://github.com/stnolting/neorv32/blob/main/CONTRIBUTING.md).
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### Key Features
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- [x] all-in-one package: **CPU** + **SoC** + **Software Framework & Tooling**
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- [x] completely described in behavioral, platform-independent VHDL - **no** platform-specific primitives, macros, attributes, etc.; an all-Verilog "version" is also [available](https://github.com/stnolting/neorv32-verilog)
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- [x] extensive configuration options for adapting the processor to the requirements of the application (on CPU, processor and system level)
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- [x] aims to be as small as possible while being as RISC-V-compliant as possible - with a reasonable area-vs-performance trade-off
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- [x] FPGA friendly (e.g. _all_ internal memories can be mapped to block RAM - including the CPU's register file)
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- [x] optimized for high clock frequencies to ease integration / timing closure
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- [x] from zero to _"hello world!"_ - completely open source and documented (on software and hardware side)
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- [x] easy to use even for FPGA / RISC-V starters – intended to work _out of the box_
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### Project Status
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[](https://github.com/stnolting/neorv32/releases)
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[](https://github.com/stnolting/neorv32/activity)
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| Task / Subproject | Repository | CI Status |
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|:------------------|:-----------|:----------|
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| Code quality ([Linty](https://linty-services.com)) | [neorv32](https://github.com/stnolting/neorv32) | [](https://oss.linty-services.com/dashboard?id=neorv32) |
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| GitHub pages (docs) | [neorv32](https://github.com/stnolting/neorv32) | [](https://stnolting.github.io/neorv32) |
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| Build documentation | [neorv32](https://github.com/stnolting/neorv32) | [](https://github.com/stnolting/neorv32/actions?query=workflow%3ADocumentation) |
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| Processor verification | [neorv32](https://github.com/stnolting/neorv32) | [](https://github.com/stnolting/neorv32/actions?query=workflow%3AProcessor) |
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| VUnit testbench | [neorv32-vunit](https://github.com/stnolting/neorv32-vunit) | [](https://github.com/stnolting/neorv32-vunit/actions/workflows/vunit.yml) |
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| RISCOF core verification | [neorv32-riscof](https://github.com/stnolting/neorv32-riscof) | [](https://github.com/stnolting/neorv32-riscof/actions/workflows/main.yml) |
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| FPGA implementations | [neorv32-setups](https://github.com/stnolting/neorv32-setups) | [](https://github.com/stnolting/neorv32-setups/actions?query=workflow%3AImplementation) |
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| All-Verilog version | [neorv32-verilog](https://github.com/stnolting/neorv32-verilog) | [](https://github.com/stnolting/neorv32-verilog/actions/workflows/main.yml) |
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| FreeRTOS port | [neorv32-freertos](https://github.com/stnolting/neorv32-freertos) | [](https://github.com/stnolting/neorv32-freertos/actions/workflows/main.yml) |
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| Prebuilt GCC toolchains | [riscv-gcc-prebuilt](https://github.com/stnolting/riscv-gcc-prebuilt) | [](https://github.com/stnolting/riscv-gcc-prebuilt/actions/workflows/main.yml) |
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The processor passes the official RISC-V architecture tests to ensure compatibility with the RISC-V ISA specs., which is checked by the
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[neorv32-riscof](https://github.com/stnolting/neorv32-riscof) repository. It can successfully run _any_ C program
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(for example from the [`sw/example`](https://github.com/stnolting/neorv32/tree/main/sw/example) folder) including CoreMark
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and FreeRTOS and can be synthesized for _any_ target technology - [tested](https://github.com/stnolting/neorv32-setups)
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on Intel, AMD, Cologne Chip and Lattice FPGAs. The conversion into a single, plain-Verilog module file is automatically checked by the
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[neorv32-verilog](https://github.com/stnolting/neorv32-verilog) repository.
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## 2. Features
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The NEORV32 Processor provides a full-featured microcontroller-like SoC build around the NEORV32 CPU.
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By using generics the design is highly configurable and allows a flexible customization to tailor the
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setup according to your needs. Note that all of the following SoC modules are entirely _optional_.
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**CPU Core**
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* [](https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)
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* RISC-V 32-bit little-endian single-core pipelined/multi-cycle modified Harvard architecture
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* configurable [instruction sets and extensions](https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions):
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\
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`RV32`
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[[`I`](https://stnolting.github.io/neorv32/#_i_isa_extension)/[`E`](https://stnolting.github.io/neorv32/#_e_isa_extension)]
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[[`M`](https://stnolting.github.io/neorv32/#_m_isa_extension)]
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[[`C`](https://stnolting.github.io/neorv32/#_c_isa_extension)]
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[[`B`](https://stnolting.github.io/neorv32/#_b_isa_extension)]
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[[`U`](https://stnolting.github.io/neorv32/#_u_isa_extension)]
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[[`X`](https://stnolting.github.io/neorv32/#_x_isa_extension)]
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[[`Zalrsc`](https://stnolting.github.io/neorv32/#_zalrsc_isa_extension)]
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[[`Zba`](https://stnolting.github.io/neorv32/#_zba_isa_extension)]
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[[`Zbb`](https://stnolting.github.io/neorv32/#_zbb_isa_extension)]
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[[`Zbkb`](https://stnolting.github.io/neorv32/#_zbkb_isa_extension)]
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[[`Zbkc`](https://stnolting.github.io/neorv32/#_zbkc_isa_extension)]
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[[`Zbkx`](https://stnolting.github.io/neorv32/#_zbkx_isa_extension)]
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[[`Zbs`](https://stnolting.github.io/neorv32/#_zbs_isa_extension)]
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[[`Zicntr`](https://stnolting.github.io/neorv32/#_zicntr_isa_extension)]
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[[`Zicond`](https://stnolting.github.io/neorv32/#_zicond_isa_extension)]
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[[`Zicsr`](https://stnolting.github.io/neorv32/#_zicsr_isa_extension)]
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[[`Zifencei`](https://stnolting.github.io/neorv32/#_zifencei_isa_extension)]
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[[`Zihpm`](https://stnolting.github.io/neorv32/#_zihpm_isa_extension)]
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[[`Zfinx`](https://stnolting.github.io/neorv32/#_zfinx_isa_extension)]
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[[`Zkn`](https://stnolting.github.io/neorv32/#_zkn_isa_extension)]
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[[`Zknd`](https://stnolting.github.io/neorv32/#_zknd_isa_extension)]
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[[`Zkne`](https://stnolting.github.io/neorv32/#_zkne_isa_extension)]
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[[`Zknh`](https://stnolting.github.io/neorv32/#_zknh_isa_extension)]
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[[`Zkt`](https://stnolting.github.io/neorv32/#_zkt_isa_extension)]
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[[`Zks`](https://stnolting.github.io/neorv32/#_zks_isa_extension)]
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[[`Zksed`](https://stnolting.github.io/neorv32/#_zksed_isa_extension)]
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[[`Zksh`](https://stnolting.github.io/neorv32/#_zksh_isa_extension)]
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[[`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_isa_extension)]
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[[`Zxcfu`](https://stnolting.github.io/neorv32/#_zxcfu_isa_extension)]
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[[`Sdext`](https://stnolting.github.io/neorv32/#_sdext_isa_extension)]
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[[`Sdtrig`](https://stnolting.github.io/neorv32/#_sdtrig_isa_extension)]
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[[`Smpmp`](https://stnolting.github.io/neorv32/#_smpmp_isa_extension)]
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* compatible to subsets of the RISC-V
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*Unprivileged ISA Specification* ([pdf](https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-spec.pdf))
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and *Privileged Architecture Specification* ([pdf](https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-privileged.pdf)).
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* `machine` and `user` privilege modes
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* implements **all** standard RISC-V exceptions and interrupts + 16 fast interrupt request channels as NEORV32-specific extension
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* custom functions unit ([CFU](https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu) as `Zxcfu` ISA extension)
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for **custom RISC-V instructions**;
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* _intrinsic_ libraries for CPU extensions that are not yet supported by GCC
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**Memories**
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* processor-internal data and instruction memories ([DMEM](https://stnolting.github.io/neorv32/#_data_memory_dmem) /
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[IMEM](https://stnolting.github.io/neorv32/#_instruction_memory_imem)) &
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caches ([iCACHE](https://stnolting.github.io/neorv32/#_processor_internal_instruction_cache_icache) and
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[dCACHE](https://stnolting.github.io/neorv32/#_processor_internal_data_cache_dcache))
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* pre-installed bootloader ([BOOTLDROM](https://stnolting.github.io/neorv32/#_bootloader_rom_bootrom)) with serial user interface;
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allows booting application code via UART or from external SPI flash
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**Timers and Counters**
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* 64-bit machine timer ([MTIME](https://stnolting.github.io/neorv32/#_machine_system_timer_mtime)), RISC-V spec. compatible
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* 32-bit general purpose timer ([GPTMR](https://stnolting.github.io/neorv32/#_general_purpose_timer_gptmr))
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* watchdog timer ([WDT](https://stnolting.github.io/neorv32/#_watchdog_timer_wdt))
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**Input / Output**
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* standard serial interfaces
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([UART](https://stnolting.github.io/neorv32/#_primary_universal_asynchronous_receiver_and_transmitter_uart0),
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[SPI](https://stnolting.github.io/neorv32/#_serial_peripheral_interface_controller_spi) (SPI host),
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[SDI](https://stnolting.github.io/neorv32/#_serial_data_interface_controller_sdi) (SPI device),
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[TWI/I²C](https://stnolting.github.io/neorv32/#_two_wire_serial_interface_controller_twi),
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[ONEWIRE/1-Wire](https://stnolting.github.io/neorv32/#_one_wire_serial_interface_controller_onewire))
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* general purpose IOs ([GPIO](https://stnolting.github.io/neorv32/#_general_purpose_input_and_output_port_gpio)) and
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[PWM](https://stnolting.github.io/neorv32/#_pulse_width_modulation_controller_pwm)
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* smart LED interface ([NEOLED](https://stnolting.github.io/neorv32/#_smart_led_interface_neoled)) to directly control NeoPixel(TM) LEDs
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**SoC Connectivity**
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* 32-bit external bus interface - Wishbone b4 compatible
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([XBUS](https://stnolting.github.io/neorv32/#_processor_external_bus_interface_xbus)) with optional cache (XCACHE);
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[wrappers](https://github.com/stnolting/neorv32/blob/main/rtl/system_integration) for AXI4-Lite and Avalon-MM host interfaces
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* stream link interface with independent RX and TX channels - AXI4-Stream compatible
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([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink))
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* external interrupts controller with up to 32 channels
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([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq))
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**Advanced**
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* true-random number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng)) based
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on the [neoTRNG](https://github.com/stnolting/neoTRNG)
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* execute-in-place module ([XIP](https://stnolting.github.io/neorv32/#_execute_in_place_module_xip)) to execute code right out of a SPI flash
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* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
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for custom tightly-coupled co-processors, accelerators or interfaces
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* direct memory access controller ([DMA](https://stnolting.github.io/neorv32/#_direct_memory_access_controller_dma)) for CPU-independent
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data transfers and conversions
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* cyclic redundancy check unit ([CRC](https://stnolting.github.io/neorv32/#_cyclic_redundancy_check_crc)) to test
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data integrity (CRC8/16/32)
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**Debugging**
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* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) accessible via standard JTAG interface
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* compatible to the "Minimal RISC-V Debug Specification Version 1.0"
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* compatible with **OpenOCD**, **GDB** and **Segger Embedded Studio**
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* RISC-V [trigger module](https://stnolting.github.io/neorv32/#_trigger_module) for hardware-assisted breakpoints
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* optional authentication module to implement custom security mechanisms
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## 3. FPGA Implementation Results
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Implementation results for **exemplary CPU configurations** generated for an Intel Cyclone IV `EP4CE22F17C6` FPGA
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using Intel Quartus Prime Lite 21.1 (no timing constrains, _balanced optimization_, f_max from _Slow 1200mV 0C Model_).
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| CPU Configuration (version [1.7.8.5](https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md)) | LEs | FFs | Memory bits | DSPs | f_max |
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|:-----------------------|:----:|:----:|:----:|:-:|:-------:|
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| `rv32i_Zicsr` | 1223 | 607 | 1024 | 0 | 130 MHz |
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| `rv32i_Zicsr_Zicntr` | 1578 | 773 | 1024 | 0 | 130 MHz |
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| `rv32imc_Zicsr_Zicntr` | 2338 | 992 | 1024 | 0 | 130 MHz |
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An incremental list of CPU extensions and processor modules can be found in the [Data Sheet: FPGA Implementation Results](https://stnolting.github.io/neorv32/#_fpga_implementation_results).
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## 4. Performance
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The NEORV32 CPU is based on a two-stages pipelined/multi-cycle architecture (fetch and execute).
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The following table shows the performance results (scores and average CPI) for exemplary CPU configurations (no caches) executing
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2000 iterations of the [CoreMark](https://github.com/stnolting/neorv32/blob/main/sw/example/coremark) CPU benchmark
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(using plain GCC10 rv32i built-in libraries only!).
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| CPU Configuration (version [1.5.7.10](https://github.com/stnolting/neorv32/blob/main/CHANGELOG.md)) | CoreMark Score |
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|:---------------------------------------------------------|:-----:|
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| _small_ (`rv32i_Zicsr_Zifencei`) | 33.89 |
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| _medium_ (`rv32imc_Zicsr_Zifencei`) | 62.50 |
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| _performance_ (`rv32imc_Zicsr_Zifencei` + perf. options) | 95.23 |
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More information regarding the CPU performance can be found in the
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[Data Sheet: CPU Performance](https://stnolting.github.io/neorv32/#_cpu_performance).
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The CPU & SoC provide further "tuning" options to optimize the design for maximum performance,
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maximum clock speed, minimal area or minimal power consumption:
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[User Guide: Application-Specific Processor Configuration](https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration)
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## 5. Getting Started
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This overview provides some *quick links* to the most important sections of the
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[online Data Sheet](https://stnolting.github.io/neorv32) and the [online User Guide](https://stnolting.github.io/neorv32/ug).
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### :mag: [NEORV32 Project](https://stnolting.github.io/neorv32/#_overview) - An Introduction
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* [Rationale](https://stnolting.github.io/neorv32/#_rationale) - why? how come? what for?
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* [Key Features](https://stnolting.github.io/neorv32/#_project_key_features) - what makes it special
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* [Structure](https://stnolting.github.io/neorv32/#_project_folder_structure) - folders, RTL files and compile order
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* [File-List Files](https://stnolting.github.io/neorv32/#_file_list_files) - to simplify HDL setup
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* [Metrics](https://stnolting.github.io/neorv32/#_fpga_implementation_results) - FPGA implementation and performance evaluation
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### :desktop_computer: [NEORV32 Processor](https://stnolting.github.io/neorv32/#_neorv32_processor_soc) - The SoC
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* [Top Entity - Signals](https://stnolting.github.io/neorv32/#_processor_top_entity_signals) - how to connect to the processor
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* [Top Entity - Generics](https://stnolting.github.io/neorv32/#_processor_top_entity_generics) - processor/CPU configuration options
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* [Address Space](https://stnolting.github.io/neorv32/#_address_space) - memory layout and boot configurations
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* [SoC Modules](https://stnolting.github.io/neorv32/#_processor_internal_modules) - IO/peripheral modules and memories
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* [On-Chip Debugger](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd) - in-system debugging of the processor via JTAG
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### :abacus: [NEORV32 CPU](https://stnolting.github.io/neorv32/#_neorv32_central_processing_unit_cpu) - The Core
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* [RISC-V Compatibility](https://stnolting.github.io/neorv32/#_risc_v_compatibility) - what is compatible to the specs and what is not
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* [Architecture](https://stnolting.github.io/neorv32/#_architecture) - a look under the hood
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* [Full Virtualization](https://stnolting.github.io/neorv32/#_full_virtualization) - execution safety
|
||
* [ISA and Extensions](https://stnolting.github.io/neorv32/#_instruction_sets_and_extensions) - available (RISC-V) ISA extensions
|
||
* [CSRs](https://stnolting.github.io/neorv32/#_control_and_status_registers_csrs) - control and status registers
|
||
* [Traps](https://stnolting.github.io/neorv32/#_traps_exceptions_and_interrupts) - interrupts and exceptions
|
||
|
||
### :floppy_disk: [Software Framework](https://stnolting.github.io/neorv32/#_software_framework) - The Software Ecosystem
|
||
|
||
* [Example Programs](https://github.com/stnolting/neorv32/tree/main/sw/example) - examples how to use the processor's IO/peripheral modules
|
||
* [Core Libraries](https://stnolting.github.io/neorv32/#_core_libraries) - high-level functions for accessing the processor's peripherals
|
||
* [Software Framework Documentation](https://stnolting.github.io/neorv32/sw/files.html) - _doxygen_-based
|
||
* [Application Makefile](https://stnolting.github.io/neorv32/#_application_makefile) - turning _your_ application into an executable
|
||
* [Bootloader](https://stnolting.github.io/neorv32/#_bootloader) - the build-in NEORV32 bootloader
|
||
* [Image Generator](https://stnolting.github.io/neorv32/#_executable_image_format) - create (FPGA) memory initialization files from your application
|
||
|
||
### :rocket: [User Guide](https://stnolting.github.io/neorv32/ug/) - Let's Get It Started
|
||
|
||
* [Toolchain Setup](https://stnolting.github.io/neorv32/ug/#_software_toolchain_setup) - install and set up the RISC-V GCC toolchain
|
||
* [General Hardware Setup](https://stnolting.github.io/neorv32/ug/#_general_hardware_setup) - set up a new NEORV32 FPGA project
|
||
* [General Software Setup](https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup) - configure the software framework
|
||
* [Application Compilation](https://stnolting.github.io/neorv32/ug/#_application_program_compilation) - compile an application using _make_
|
||
* [Upload via Bootloader](https://stnolting.github.io/neorv32/ug/#_uploading_and_starting_of_a_binary_executable_image_via_uart) - upload and execute executables
|
||
* [Application-Specific Processor Configuration](https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration) - tailor the processor to your needs
|
||
* [Adding Custom Hardware Modules](https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules) - add _your_ custom hardware
|
||
* [Debugging via the On-Chip Debugger](https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger) - step through code *online* and *in-system*
|
||
* [Simulation](https://stnolting.github.io/neorv32/ug/#_simulating_the_processor) - simulate the whole SoC
|
||
* [LiteX Integration](https://stnolting.github.io/neorv32/ug/#_litex_soc_builder_support) - build a SoC using NEORV32 + [LiteX](https://github.com/enjoy-digital/litex)
|
||
* [Convert to Verilog](https://stnolting.github.io/neorv32/ug/#_neorv32_in_verilog) - turn the NEORV32 into an all-Verilog design
|
||
* [Package as Vivado IP block](https://stnolting.github.io/neorv32/ug/#_packaging_the_processor_as_vivado_ip_block) - turn the entire processor into an interactive AMD Vivado IP block
|
||
* [Using Eclipse](https://stnolting.github.io/neorv32/ug/#_eclipse_ide) - use the Eclipse IDE for developing and debugging
|
||
|
||
### :copyright: Legal
|
||
|
||
[](https://github.com/stnolting/neorv32/blob/main/LICENSE)
|
||
[](https://doi.org/10.5281/zenodo.5018888)
|
||
|
||
* [Overview](https://stnolting.github.io/neorv32/#_legal) - license, disclaimer, limitation of liability for external links, proprietary notice, etc.
|
||
* [Citing](https://stnolting.github.io/neorv32/#_citing) - citing information
|
||
|
||
This is an open-source project that is free of charge. Use this project in any way you like
|
||
(as long as it complies to the permissive [license](https://github.com/stnolting/neorv32/blob/main/LICENSE)).
|
||
Please cite it appropriately. :+1:
|
||
|
||
|
||
---------------------------------------
|
||
|
||
**:heart: A big shout-out to the community and all the [contributors](https://github.com/stnolting/neorv32/graphs/contributors) -
|
||
this project would not be where it is without them!**
|