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serv/rtl
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Olof Kindgren 2b7bddbb08 pre/post works. mem broken
2022-01-14 23:36:20 +01:00
..
serv_alu.v Rewrite logic expression of alu bool operations 2021-05-15 23:07:55 +02:00
serv_bufreg.v Simplify optional MDU logic 2021-10-03 23:28:45 +02:00
serv_bufreg2.v Move dbus_dat/rs2/shamt storage to bufreg2 2022-01-02 22:10:33 +01:00
serv_csr.v Add reset for new_irq register 2021-08-27 13:10:06 +02:00
serv_ctrl.v Syntax fixes 2021-01-18 22:47:28 +01:00
serv_decode.v pre/post works. mem broken 2022-01-14 23:36:20 +01:00
serv_immdec.v updated vars declaration for modelsim (#63) 2021-10-03 23:15:54 +02:00
serv_mem_decode.v pre/post works. mem broken 2022-01-14 23:36:20 +01:00
serv_mem_if.v Move dbus_dat/rs2/shamt storage to bufreg2 2022-01-02 22:10:33 +01:00
serv_post_reg_decode.v pre/post works. mem broken 2022-01-14 23:36:20 +01:00
serv_pre_reg_decode.v pre/post works. mem broken 2022-01-14 23:36:20 +01:00
serv_rf_if.v Add missing gate on mem_rd with CSR disabled 2021-12-29 00:17:00 +01:00
serv_rf_ram.v Always return 0 from reads to reg x0 in serv_rf_ram 2021-08-27 13:10:06 +02:00
serv_rf_ram_if.v Remove unused wgo register 2021-04-08 15:36:11 +02:00
serv_rf_top.v M-extension support for SERV 2021-08-20 23:45:19 +02:00
serv_state.v Simplify branch_op/slt_op signals 2021-10-08 22:25:24 +02:00
serv_synth_wrapper.v Added openlane target and params.tcl with suitable openlane parameters for SERV 2021-08-30 22:13:42 +02:00
serv_top.v pre/post works. mem broken 2022-01-14 23:36:20 +01:00