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temp files cleanup

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This commit is contained in:
Blaise Tine 2020-03-09 10:18:11 -04:00
parent 717a75ade8
commit 36547821fc
146 changed files with 39 additions and 5330891 deletions
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4
benchmarks/vector/saxpy/Makefile
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@ -31,3 +31,7 @@ HEX: ELF
ELF:
$(COMP) $(CC_FLAGS) $(VX_STR) $(VX_VEC) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_TEST) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf
clean:
rm -rf *.o *.elf *.dump *.hex *.qemu *.log *.debug

92920
benchmarks/vector/saxpy/vx_vec_saxpy.dump
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BIN
benchmarks/vector/saxpy/vx_vec_saxpy.elf
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benchmarks/vector/saxpy/vx_vec_saxpy.hex
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3
benchmarks/vector/sfilter/Makefile
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@ -31,3 +31,6 @@ HEX: ELF
ELF:
$(COMP) $(CC_FLAGS) $(VX_STR) $(VX_VEC) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_TEST) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf
clean:
rm -rf *.o *.elf *.dump *.hex *.qemu *.log *.debug

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benchmarks/vector/sfilter/vx_vec_sfilter.dump
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benchmarks/vector/sfilter/vx_vec_sfilter.elf
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benchmarks/vector/sfilter/vx_vec_sfilter.hex
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3
benchmarks/vector/sgemm_nn/Makefile
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@ -31,3 +31,6 @@ HEX: ELF
ELF:
$(COMP) $(CC_FLAGS) $(VX_STR) $(VX_VEC) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_TEST) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf
clean:
rm -rf *.o *.elf *.dump *.hex *.qemu *.log *.debug

87138
benchmarks/vector/sgemm_nn/vx_vec_sgemm_nn.dump
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benchmarks/vector/sgemm_nn/vx_vec_sgemm_nn.elf
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benchmarks/vector/sgemm_nn/vx_vec_sgemm_nn.hex
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3
benchmarks/vector/vecadd/Makefile
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@ -39,3 +39,6 @@ ELF:
# $(COMP) $(CC_FLAGS) $(VX_STR) $(VX_VEC3) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_TEST) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf
# $(COMP) $(CC_FLAGS) $(VX_STR) $(VX_VEC4) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_TEST) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf
# $(COMP) $(CC_FLAGS) $(VX_STR) $(VX_VEC5) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_TEST) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf~
clean:
rm -rf *.o *.elf *.dump *.hex *.qemu *.log *.debug

86984
benchmarks/vector/vecadd/vx_vec_vecadd.dump
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benchmarks/vector/vecadd/vx_vec_vecadd.elf
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benchmarks/vector/vecadd/vx_vec_vecadd.hex
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2
rtl/Makefile
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@ -49,4 +49,4 @@ w: VERILATORnoWarnings
$(MAKECPP)
clean:
rm obj_dir/*
rm -rf obj_dir

3
runtime/mains/dev/Makefile
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@ -29,3 +29,6 @@ HEX: ELF
ELF:
$(COMP) $(CC_FLAGS) $(VX_STR) $(VX_INT) $(VX_IO) $(VX_API) $(VX_TEST) $(VX_MAIN) -o vx_dev_main.elf
clean:
rm -rf *.o *.elf *.dump *.hex *.qemu *.log *.debug

86963
runtime/mains/dev/vx_dev_main.dump
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runtime/mains/dev/vx_dev_main.elf
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runtime/mains/dev/vx_dev_main.hex
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3
runtime/mains/hello/Makefile
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@ -28,3 +28,6 @@ HEX: ELF
ELF:
$(COMP) $(CC_FLAGS) $(VX_STR) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_TEST) $(VX_MAIN).cpp $(LIBS) -Iinclude -o $(VX_MAIN).elf
clean:
rm -rf *.o *.elf *.dump *.hex *.qemu *.log *.debug

1031
runtime/mains/hello/hello.dump
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runtime/mains/hello/hello.elf
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262
runtime/mains/hello/hello.hex
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@ -1,262 +0,0 @@
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3
runtime/mains/nativevecadd/Makefile
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@ -32,3 +32,6 @@ HEX: ELF
ELF:
$(COMP) $(CC_FLAGS) $(VX_STR) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_TEST) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf
clean:
rm -rf *.o *.elf *.dump *.hex *.qemu *.log *.debug

1468097
runtime/mains/nativevecadd/libs/libopencl.dump
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runtime/mains/nativevecadd/libs/libvecadd.dump
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@ -1,420 +0,0 @@
In archive libvecadd.a:
tempfile-56-19-33-68-f2.o: file format elf32-littleriscv
Disassembly of section .text:
00000000 <__cxx_global_var_init>:
0: ff010113 addi sp,sp,-16
4: 00112623 sw ra,12(sp)
8: 00812423 sw s0,8(sp)
c: 01010413 addi s0,sp,16
10: 00000537 lui a0,0x0
14: 00050513 mv a0,a0
18: 00000097 auipc ra,0x0
1c: 000080e7 jalr ra # 18 <__cxx_global_var_init+0x18>
20: 00812403 lw s0,8(sp)
24: 00c12083 lw ra,12(sp)
28: 01010113 addi sp,sp,16
2c: 00008067 ret
00000030 <_ZN12_GLOBAL__N_122auto_register_kernel_tC2Ev>:
30: ff010113 addi sp,sp,-16
34: 00112623 sw ra,12(sp)
38: 00812423 sw s0,8(sp)
3c: 01010413 addi s0,sp,16
40: fea42a23 sw a0,-12(s0)
44: 00000537 lui a0,0x0
48: 00050513 mv a0,a0
4c: 000005b7 lui a1,0x0
50: 00058593 mv a1,a1
54: 00000637 lui a2,0x0
58: 00060713 mv a4,a2
5c: 00000637 lui a2,0x0
60: 00060793 mv a5,a2
64: 00300613 li a2,3
68: 00000693 li a3,0
6c: 00000097 auipc ra,0x0
70: 000080e7 jalr ra # 6c <_ZN12_GLOBAL__N_122auto_register_kernel_tC2Ev+0x3c>
74: 00812403 lw s0,8(sp)
78: 00c12083 lw ra,12(sp)
7c: 01010113 addi sp,sp,16
80: 00008067 ret
00000084 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc>:
84: ff010113 addi sp,sp,-16
88: 00112623 sw ra,12(sp)
8c: 00812423 sw s0,8(sp)
90: 01010413 addi s0,sp,16
94: 00000097 auipc ra,0x0
98: 000080e7 jalr ra # 94 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0x10>
9c: 00812403 lw s0,8(sp)
a0: 00c12083 lw ra,12(sp)
a4: 01010113 addi sp,sp,16
a8: 00008067 ret
Disassembly of section .sbss:
00000000 <_ZN12_GLOBAL__N_15__x__E>:
...
Disassembly of section .sdata:
00000000 <_ZZN12_GLOBAL__N_122auto_register_kernel_tC1EvE9arg_types>:
0: 0101 addi sp,sp,0
2: 01 Address 0x0000000000000002 is out of bounds.
Disassembly of section .bss:
00000000 <_ZZN12_GLOBAL__N_122auto_register_kernel_tC1EvE11local_sizes>:
...
Disassembly of section .rodata.str1.1:
00000000 <.L.str>:
0: 6576 flw fa0,92(sp)
2: 64646163 bltu s0,t1,644 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0x5c0>
...
Disassembly of section .init_array:
00000000 <.init_array>:
0: 0000 unimp
...
Disassembly of section .comment:
00000000 <.comment>:
0: 6300 flw fs0,0(a4)
2: 616c flw fa1,68(a0)
4: 676e flw fa4,216(sp)
6: 7620 flw fs0,104(a2)
8: 7265 lui tp,0xffff9
a: 6e6f6973 csrrsi s2,0x6e6,30
e: 3920 fld fs0,112(a0)
10: 302e fld ft0,232(sp)
12: 312e fld ft2,232(sp)
14: 2820 fld fs0,80(s0)
16: 7468 flw fa0,108(s0)
18: 7074 flw fa3,100(s0)
1a: 2f2f3a73 csrrc s4,0x2f2,t5
1e: 68746967 0x68746967
22: 6275 lui tp,0x1d
24: 632e flw ft6,200(sp)
26: 6c2f6d6f jal s10,f66e8 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xf6664>
2a: 766c flw fa1,108(a2)
2c: 2d6d jal 6e6 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0x662>
2e: 696d lui s2,0x1b
30: 7272 flw ft4,60(sp)
32: 632f726f jal tp,f7664 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xf75e0>
36: 616c flw fa1,68(a0)
38: 676e flw fa4,216(sp)
3a: 672e flw fa4,200(sp)
3c: 7469 lui s0,0xffffa
3e: 6220 flw fs0,64(a2)
40: 6465 lui s0,0x19
42: 34643733 0x34643733
46: 3162 fld ft2,56(sp)
48: 6338 flw fa4,64(a4)
4a: 3665 jal fffffbf2 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xfffffb6e>
4c: 3939 jal fffffc6a <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xfffffbe6>
4e: 32636633 0x32636633
52: 3635 jal fffffb7e <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xfffffafa>
54: 64386537 lui a0,0x64386
58: 3665 jal fffffc00 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xfffffb7c>
5a: 6631 lui a2,0xc
5c: 6236 flw ft4,76(sp)
5e: 64663033 0x64663033
62: 6330 flw fa2,64(a4)
64: 3762 fld fa4,56(sp)
66: 2935 jal 4a2 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0x41e>
68: 2820 fld fs0,80(s0)
6a: 7468 flw fa0,108(s0)
6c: 7074 flw fa3,100(s0)
6e: 2f2f3a73 csrrc s4,0x2f2,t5
72: 68746967 0x68746967
76: 6275 lui tp,0x1d
78: 632e flw ft6,200(sp)
7a: 6c2f6d6f jal s10,f673c <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xf66b8>
7e: 766c flw fa1,108(a2)
80: 2d6d jal 73a <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0x6b6>
82: 696d lui s2,0x1b
84: 7272 flw ft4,60(sp)
86: 6c2f726f jal tp,f7748 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xf76c4>
8a: 766c flw fa1,108(a2)
8c: 2e6d jal 446 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0x3c2>
8e: 20746967 0x20746967
92: 35663263 0x35663263
96: 62393033 0x62393033
9a: 3132 fld ft2,296(sp)
9c: 6336 flw ft6,76(sp)
9e: 3062 fld ft0,56(sp)
a0: 6132 flw ft2,12(sp)
a2: 6130 flw fa2,64(a0)
a4: 6561 lui a0,0x18
a6: 3731 jal ffffffb2 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xffffff2e>
a8: 35333533 0x35333533
ac: 3934 fld fa3,112(a0)
ae: 3964 fld fs1,240(a0)
b0: 3538 fld fa4,104(a0)
b2: 3562 fld fa0,56(sp)
b4: 3062 fld ft0,56(sp)
b6: 3635 jal fffffbe2 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xfffffb5e>
b8: 00293533 sltu a0,s2,sp
Disassembly of section .llvm_addrsig:
00000000 <.llvm_addrsig>:
0: 0a08 addi a0,sp,272
2: 0309 addi t1,t1,2
4: 0705 addi a4,a4,1
6: 06 Address 0x0000000000000006 is out of bounds.
tempfile-36-3d-1d-4c-cd.so.o: file format elf32-littleriscv
Disassembly of section .text:
00000000 <_pocl_kernel_vecadd>:
0: fe010113 addi sp,sp,-32
4: 00112e23 sw ra,28(sp)
8: 00812c23 sw s0,24(sp)
c: 00912a23 sw s1,20(sp)
10: 01212823 sw s2,16(sp)
14: 01312623 sw s3,12(sp)
18: 01412423 sw s4,8(sp)
1c: 01512223 sw s5,4(sp)
20: 02010413 addi s0,sp,32
24: ffc17113 andi sp,sp,-4
28: 00068913 mv s2,a3
2c: 00060993 mv s3,a2
30: 00058a13 mv s4,a1
34: 00050a93 mv s5,a0
38: 0186a483 lw s1,24(a3)
3c: 00048513 mv a0,s1
40: 00070593 mv a1,a4
44: 00000097 auipc ra,0x0
48: 000080e7 jalr ra # 44 <_pocl_kernel_vecadd+0x44>
4c: 00c92583 lw a1,12(s2)
50: 00a58533 add a0,a1,a0
54: 00251513 slli a0,a0,0x2
58: 00aa82b3 add t0,s5,a0
5c: 00aa0333 add t1,s4,a0
60: 00a983b3 add t2,s3,a0
64: 02092803 lw a6,32(s2)
68: 01c92e03 lw t3,28(s2)
6c: 00000893 li a7,0
70: 00000e93 li t4,0
74: 00028513 mv a0,t0
78: 00030593 mv a1,t1
7c: 00038613 mv a2,t2
80: 00000793 li a5,0
84: 00052703 lw a4,0(a0)
88: 0005a683 lw a3,0(a1)
8c: 00e686b3 add a3,a3,a4
90: 00d62023 sw a3,0(a2)
94: 00450513 addi a0,a0,4
98: 00458593 addi a1,a1,4
9c: 00460613 addi a2,a2,4
a0: 00178793 addi a5,a5,1
a4: fe97e0e3 bltu a5,s1,84 <_pocl_kernel_vecadd+0x84>
a8: 001e8e93 addi t4,t4,1
ac: fdcee4e3 bltu t4,t3,74 <_pocl_kernel_vecadd+0x74>
b0: 00188893 addi a7,a7,1
b4: fb08eee3 bltu a7,a6,70 <_pocl_kernel_vecadd+0x70>
b8: fe040113 addi sp,s0,-32
bc: 00412a83 lw s5,4(sp)
c0: 00812a03 lw s4,8(sp)
c4: 00c12983 lw s3,12(sp)
c8: 01012903 lw s2,16(sp)
cc: 01412483 lw s1,20(sp)
d0: 01812403 lw s0,24(sp)
d4: 01c12083 lw ra,28(sp)
d8: 02010113 addi sp,sp,32
dc: 00008067 ret
000000e0 <_pocl_kernel_vecadd_workgroup>:
e0: ff010113 addi sp,sp,-16
e4: 00112623 sw ra,12(sp)
e8: 00812423 sw s0,8(sp)
ec: 00912223 sw s1,4(sp)
f0: 01212023 sw s2,0(sp)
f4: 00058493 mv s1,a1
f8: 00050913 mv s2,a0
fc: 0185a403 lw s0,24(a1)
100: 00040513 mv a0,s0
104: 00060593 mv a1,a2
108: 00000097 auipc ra,0x0
10c: 000080e7 jalr ra # 108 <_pocl_kernel_vecadd_workgroup+0x28>
110: 00c4a583 lw a1,12(s1)
114: 00a58533 add a0,a1,a0
118: 00251513 slli a0,a0,0x2
11c: 00892583 lw a1,8(s2)
120: 0005a583 lw a1,0(a1)
124: 00492603 lw a2,4(s2)
128: 00062603 lw a2,0(a2)
12c: 00092683 lw a3,0(s2)
130: 0006a683 lw a3,0(a3)
134: 00a682b3 add t0,a3,a0
138: 00a60333 add t1,a2,a0
13c: 00a583b3 add t2,a1,a0
140: 0204a803 lw a6,32(s1)
144: 01c4ae03 lw t3,28(s1)
148: 00000893 li a7,0
14c: 00000493 li s1,0
150: 00028513 mv a0,t0
154: 00030593 mv a1,t1
158: 00038613 mv a2,t2
15c: 00000793 li a5,0
160: 00052683 lw a3,0(a0)
164: 0005a703 lw a4,0(a1)
168: 00d706b3 add a3,a4,a3
16c: 00d62023 sw a3,0(a2)
170: 00450513 addi a0,a0,4
174: 00458593 addi a1,a1,4
178: 00460613 addi a2,a2,4
17c: 00178793 addi a5,a5,1
180: fe87e0e3 bltu a5,s0,160 <_pocl_kernel_vecadd_workgroup+0x80>
184: 00148493 addi s1,s1,1
188: fdc4e4e3 bltu s1,t3,150 <_pocl_kernel_vecadd_workgroup+0x70>
18c: 00188893 addi a7,a7,1
190: fb08eee3 bltu a7,a6,14c <_pocl_kernel_vecadd_workgroup+0x6c>
194: 00012903 lw s2,0(sp)
198: 00412483 lw s1,4(sp)
19c: 00812403 lw s0,8(sp)
1a0: 00c12083 lw ra,12(sp)
1a4: 01010113 addi sp,sp,16
1a8: 00008067 ret
000001ac <_pocl_kernel_vecadd_workgroup_fast>:
1ac: ff010113 addi sp,sp,-16
1b0: 00112623 sw ra,12(sp)
1b4: 00812423 sw s0,8(sp)
1b8: 00912223 sw s1,4(sp)
1bc: 01212023 sw s2,0(sp)
1c0: 00058493 mv s1,a1
1c4: 00050913 mv s2,a0
1c8: 0185a403 lw s0,24(a1)
1cc: 00040513 mv a0,s0
1d0: 00060593 mv a1,a2
1d4: 00000097 auipc ra,0x0
1d8: 000080e7 jalr ra # 1d4 <_pocl_kernel_vecadd_workgroup_fast+0x28>
1dc: 00c4a583 lw a1,12(s1)
1e0: 00a58533 add a0,a1,a0
1e4: 00251513 slli a0,a0,0x2
1e8: 00892583 lw a1,8(s2)
1ec: 00492603 lw a2,4(s2)
1f0: 00092683 lw a3,0(s2)
1f4: 00a682b3 add t0,a3,a0
1f8: 00a60333 add t1,a2,a0
1fc: 00a583b3 add t2,a1,a0
200: 0204a803 lw a6,32(s1)
204: 01c4ae03 lw t3,28(s1)
208: 00000893 li a7,0
20c: 00000493 li s1,0
210: 00028513 mv a0,t0
214: 00030593 mv a1,t1
218: 00038613 mv a2,t2
21c: 00000793 li a5,0
220: 00052683 lw a3,0(a0)
224: 0005a703 lw a4,0(a1)
228: 00d706b3 add a3,a4,a3
22c: 00d62023 sw a3,0(a2)
230: 00450513 addi a0,a0,4
234: 00458593 addi a1,a1,4
238: 00460613 addi a2,a2,4
23c: 00178793 addi a5,a5,1
240: fe87e0e3 bltu a5,s0,220 <_pocl_kernel_vecadd_workgroup_fast+0x74>
244: 00148493 addi s1,s1,1
248: fdc4e4e3 bltu s1,t3,210 <_pocl_kernel_vecadd_workgroup_fast+0x64>
24c: 00188893 addi a7,a7,1
250: fb08eee3 bltu a7,a6,20c <_pocl_kernel_vecadd_workgroup_fast+0x60>
254: 00012903 lw s2,0(sp)
258: 00412483 lw s1,4(sp)
25c: 00812403 lw s0,8(sp)
260: 00c12083 lw ra,12(sp)
264: 01010113 addi sp,sp,16
268: 00008067 ret
Disassembly of section .comment:
00000000 <.comment>:
0: 6300 flw fs0,0(a4)
2: 616c flw fa1,68(a0)
4: 676e flw fa4,216(sp)
6: 7620 flw fs0,104(a2)
8: 7265 lui tp,0xffff9
a: 6e6f6973 csrrsi s2,0x6e6,30
e: 3920 fld fs0,112(a0)
10: 302e fld ft0,232(sp)
12: 312e fld ft2,232(sp)
14: 2820 fld fs0,80(s0)
16: 7468 flw fa0,108(s0)
18: 7074 flw fa3,100(s0)
1a: 2f2f3a73 csrrc s4,0x2f2,t5
1e: 68746967 0x68746967
22: 6275 lui tp,0x1d
24: 632e flw ft6,200(sp)
26: 6c2f6d6f jal s10,f66e8 <_pocl_kernel_vecadd_workgroup_fast+0xf653c>
2a: 766c flw fa1,108(a2)
2c: 2d6d jal 6e6 <_pocl_kernel_vecadd_workgroup_fast+0x53a>
2e: 696d lui s2,0x1b
30: 7272 flw ft4,60(sp)
32: 632f726f jal tp,f7664 <_pocl_kernel_vecadd_workgroup_fast+0xf74b8>
36: 616c flw fa1,68(a0)
38: 676e flw fa4,216(sp)
3a: 672e flw fa4,200(sp)
3c: 7469 lui s0,0xffffa
3e: 6220 flw fs0,64(a2)
40: 6465 lui s0,0x19
42: 34643733 0x34643733
46: 3162 fld ft2,56(sp)
48: 6338 flw fa4,64(a4)
4a: 3665 jal fffffbf2 <_pocl_kernel_vecadd_workgroup_fast+0xfffffa46>
4c: 3939 jal fffffc6a <_pocl_kernel_vecadd_workgroup_fast+0xfffffabe>
4e: 32636633 0x32636633
52: 3635 jal fffffb7e <_pocl_kernel_vecadd_workgroup_fast+0xfffff9d2>
54: 64386537 lui a0,0x64386
58: 3665 jal fffffc00 <_pocl_kernel_vecadd_workgroup_fast+0xfffffa54>
5a: 6631 lui a2,0xc
5c: 6236 flw ft4,76(sp)
5e: 64663033 0x64663033
62: 6330 flw fa2,64(a4)
64: 3762 fld fa4,56(sp)
66: 2935 jal 4a2 <_pocl_kernel_vecadd_workgroup_fast+0x2f6>
68: 2820 fld fs0,80(s0)
6a: 7468 flw fa0,108(s0)
6c: 7074 flw fa3,100(s0)
6e: 2f2f3a73 csrrc s4,0x2f2,t5
72: 68746967 0x68746967
76: 6275 lui tp,0x1d
78: 632e flw ft6,200(sp)
7a: 6c2f6d6f jal s10,f673c <_pocl_kernel_vecadd_workgroup_fast+0xf6590>
7e: 766c flw fa1,108(a2)
80: 2d6d jal 73a <_pocl_kernel_vecadd_workgroup_fast+0x58e>
82: 696d lui s2,0x1b
84: 7272 flw ft4,60(sp)
86: 6c2f726f jal tp,f7748 <_pocl_kernel_vecadd_workgroup_fast+0xf759c>
8a: 766c flw fa1,108(a2)
8c: 2e6d jal 446 <_pocl_kernel_vecadd_workgroup_fast+0x29a>
8e: 20746967 0x20746967
92: 35663263 0x35663263
96: 62393033 0x62393033
9a: 3132 fld ft2,296(sp)
9c: 6336 flw ft6,76(sp)
9e: 3062 fld ft0,56(sp)
a0: 6132 flw ft2,12(sp)
a2: 6130 flw fa2,64(a0)
a4: 6561 lui a0,0x18
a6: 3731 jal ffffffb2 <_pocl_kernel_vecadd_workgroup_fast+0xfffffe06>
a8: 35333533 0x35333533
ac: 3934 fld fa3,112(a0)
ae: 3964 fld fs1,240(a0)
b0: 3538 fld fa4,104(a0)
b2: 3562 fld fa0,56(sp)
b4: 3062 fld ft0,56(sp)
b6: 3635 jal fffffbe2 <_pocl_kernel_vecadd_workgroup_fast+0xfffffa36>
b8: 00293533 sltu a0,s2,sp

BIN
runtime/mains/nativevecadd/libs/vecadd
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494132
runtime/mains/nativevecadd/libs/vecadd.dump
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87791
runtime/mains/nativevecadd/vx_pocl_main.dump
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runtime/mains/nativevecadd/vx_pocl_main.elf
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5844
runtime/mains/nativevecadd/vx_pocl_main.hex
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3
runtime/mains/nlTest/Makefile
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@ -27,3 +27,6 @@ HEX: ELF
ELF:
$(COMP) $(CC_FLAGS) $(VX_STR) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_TEST) $(VX_MAIN) /opt/riscv/riscv32-unknown-elf/lib/libc.a /opt/riscv/riscv32-unknown-elf/lib/libstdc++.a -static-libgcc -lgcc -o vx_nl_main.elf
clean:
rm -rf *.o *.elf *.dump *.hex *.qemu *.log *.debug

76173
runtime/mains/nlTest/vx_nl_main.dump
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runtime/mains/nlTest/vx_nl_main.elf
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4675
runtime/mains/nlTest/vx_nl_main.hex
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5
runtime/mains/simple/Makefile
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@ -26,4 +26,7 @@ HEX: ELF
$(CPY) -O ihex $(VX_MAIN).elf $(VX_MAIN).hex
ELF:
$(COMP) $(CC_FLAGS) $(VX_STR) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_TEST) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf
$(COMP) $(CC_FLAGS) $(VX_STR) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_TEST) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf
clean:
rm -rf *.o *.elf *.dump *.hex *.qemu *.log *.debug

86976
runtime/mains/simple/vx_simple_main.dump
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runtime/mains/simple/vx_simple_main.elf
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5713
runtime/mains/simple/vx_simple_main.hex
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3
runtime/mains/vecadd/Makefile
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@ -32,3 +32,6 @@ HEX: ELF
ELF:
$(COMP) $(CC_FLAGS) $(VX_STR) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_TEST) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf
clean:
rm -rf *.o *.elf *.dump *.hex *.qemu *.log *.debug

1468097
runtime/mains/vecadd/libs/libopencl.dump
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420
runtime/mains/vecadd/libs/libvecadd.dump
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@ -1,420 +0,0 @@
In archive libvecadd.a:
tempfile-56-19-33-68-f2.o: file format elf32-littleriscv
Disassembly of section .text:
00000000 <__cxx_global_var_init>:
0: ff010113 addi sp,sp,-16
4: 00112623 sw ra,12(sp)
8: 00812423 sw s0,8(sp)
c: 01010413 addi s0,sp,16
10: 00000537 lui a0,0x0
14: 00050513 mv a0,a0
18: 00000097 auipc ra,0x0
1c: 000080e7 jalr ra # 18 <__cxx_global_var_init+0x18>
20: 00812403 lw s0,8(sp)
24: 00c12083 lw ra,12(sp)
28: 01010113 addi sp,sp,16
2c: 00008067 ret
00000030 <_ZN12_GLOBAL__N_122auto_register_kernel_tC2Ev>:
30: ff010113 addi sp,sp,-16
34: 00112623 sw ra,12(sp)
38: 00812423 sw s0,8(sp)
3c: 01010413 addi s0,sp,16
40: fea42a23 sw a0,-12(s0)
44: 00000537 lui a0,0x0
48: 00050513 mv a0,a0
4c: 000005b7 lui a1,0x0
50: 00058593 mv a1,a1
54: 00000637 lui a2,0x0
58: 00060713 mv a4,a2
5c: 00000637 lui a2,0x0
60: 00060793 mv a5,a2
64: 00300613 li a2,3
68: 00000693 li a3,0
6c: 00000097 auipc ra,0x0
70: 000080e7 jalr ra # 6c <_ZN12_GLOBAL__N_122auto_register_kernel_tC2Ev+0x3c>
74: 00812403 lw s0,8(sp)
78: 00c12083 lw ra,12(sp)
7c: 01010113 addi sp,sp,16
80: 00008067 ret
00000084 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc>:
84: ff010113 addi sp,sp,-16
88: 00112623 sw ra,12(sp)
8c: 00812423 sw s0,8(sp)
90: 01010413 addi s0,sp,16
94: 00000097 auipc ra,0x0
98: 000080e7 jalr ra # 94 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0x10>
9c: 00812403 lw s0,8(sp)
a0: 00c12083 lw ra,12(sp)
a4: 01010113 addi sp,sp,16
a8: 00008067 ret
Disassembly of section .sbss:
00000000 <_ZN12_GLOBAL__N_15__x__E>:
...
Disassembly of section .sdata:
00000000 <_ZZN12_GLOBAL__N_122auto_register_kernel_tC1EvE9arg_types>:
0: 0101 addi sp,sp,0
2: 01 Address 0x0000000000000002 is out of bounds.
Disassembly of section .bss:
00000000 <_ZZN12_GLOBAL__N_122auto_register_kernel_tC1EvE11local_sizes>:
...
Disassembly of section .rodata.str1.1:
00000000 <.L.str>:
0: 6576 flw fa0,92(sp)
2: 64646163 bltu s0,t1,644 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0x5c0>
...
Disassembly of section .init_array:
00000000 <.init_array>:
0: 0000 unimp
...
Disassembly of section .comment:
00000000 <.comment>:
0: 6300 flw fs0,0(a4)
2: 616c flw fa1,68(a0)
4: 676e flw fa4,216(sp)
6: 7620 flw fs0,104(a2)
8: 7265 lui tp,0xffff9
a: 6e6f6973 csrrsi s2,0x6e6,30
e: 3920 fld fs0,112(a0)
10: 302e fld ft0,232(sp)
12: 312e fld ft2,232(sp)
14: 2820 fld fs0,80(s0)
16: 7468 flw fa0,108(s0)
18: 7074 flw fa3,100(s0)
1a: 2f2f3a73 csrrc s4,0x2f2,t5
1e: 68746967 0x68746967
22: 6275 lui tp,0x1d
24: 632e flw ft6,200(sp)
26: 6c2f6d6f jal s10,f66e8 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xf6664>
2a: 766c flw fa1,108(a2)
2c: 2d6d jal 6e6 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0x662>
2e: 696d lui s2,0x1b
30: 7272 flw ft4,60(sp)
32: 632f726f jal tp,f7664 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xf75e0>
36: 616c flw fa1,68(a0)
38: 676e flw fa4,216(sp)
3a: 672e flw fa4,200(sp)
3c: 7469 lui s0,0xffffa
3e: 6220 flw fs0,64(a2)
40: 6465 lui s0,0x19
42: 34643733 0x34643733
46: 3162 fld ft2,56(sp)
48: 6338 flw fa4,64(a4)
4a: 3665 jal fffffbf2 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xfffffb6e>
4c: 3939 jal fffffc6a <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xfffffbe6>
4e: 32636633 0x32636633
52: 3635 jal fffffb7e <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xfffffafa>
54: 64386537 lui a0,0x64386
58: 3665 jal fffffc00 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xfffffb7c>
5a: 6631 lui a2,0xc
5c: 6236 flw ft4,76(sp)
5e: 64663033 0x64663033
62: 6330 flw fa2,64(a4)
64: 3762 fld fa4,56(sp)
66: 2935 jal 4a2 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0x41e>
68: 2820 fld fs0,80(s0)
6a: 7468 flw fa0,108(s0)
6c: 7074 flw fa3,100(s0)
6e: 2f2f3a73 csrrc s4,0x2f2,t5
72: 68746967 0x68746967
76: 6275 lui tp,0x1d
78: 632e flw ft6,200(sp)
7a: 6c2f6d6f jal s10,f673c <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xf66b8>
7e: 766c flw fa1,108(a2)
80: 2d6d jal 73a <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0x6b6>
82: 696d lui s2,0x1b
84: 7272 flw ft4,60(sp)
86: 6c2f726f jal tp,f7748 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xf76c4>
8a: 766c flw fa1,108(a2)
8c: 2e6d jal 446 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0x3c2>
8e: 20746967 0x20746967
92: 35663263 0x35663263
96: 62393033 0x62393033
9a: 3132 fld ft2,296(sp)
9c: 6336 flw ft6,76(sp)
9e: 3062 fld ft0,56(sp)
a0: 6132 flw ft2,12(sp)
a2: 6130 flw fa2,64(a0)
a4: 6561 lui a0,0x18
a6: 3731 jal ffffffb2 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xffffff2e>
a8: 35333533 0x35333533
ac: 3934 fld fa3,112(a0)
ae: 3964 fld fs1,240(a0)
b0: 3538 fld fa4,104(a0)
b2: 3562 fld fa0,56(sp)
b4: 3062 fld ft0,56(sp)
b6: 3635 jal fffffbe2 <_GLOBAL__sub_I_tempfile_7a_73_15_a5_2b.cc+0xfffffb5e>
b8: 00293533 sltu a0,s2,sp
Disassembly of section .llvm_addrsig:
00000000 <.llvm_addrsig>:
0: 0a08 addi a0,sp,272
2: 0309 addi t1,t1,2
4: 0705 addi a4,a4,1
6: 06 Address 0x0000000000000006 is out of bounds.
tempfile-36-3d-1d-4c-cd.so.o: file format elf32-littleriscv
Disassembly of section .text:
00000000 <_pocl_kernel_vecadd>:
0: fe010113 addi sp,sp,-32
4: 00112e23 sw ra,28(sp)
8: 00812c23 sw s0,24(sp)
c: 00912a23 sw s1,20(sp)
10: 01212823 sw s2,16(sp)
14: 01312623 sw s3,12(sp)
18: 01412423 sw s4,8(sp)
1c: 01512223 sw s5,4(sp)
20: 02010413 addi s0,sp,32
24: ffc17113 andi sp,sp,-4
28: 00068913 mv s2,a3
2c: 00060993 mv s3,a2
30: 00058a13 mv s4,a1
34: 00050a93 mv s5,a0
38: 0186a483 lw s1,24(a3)
3c: 00048513 mv a0,s1
40: 00070593 mv a1,a4
44: 00000097 auipc ra,0x0
48: 000080e7 jalr ra # 44 <_pocl_kernel_vecadd+0x44>
4c: 00c92583 lw a1,12(s2)
50: 00a58533 add a0,a1,a0
54: 00251513 slli a0,a0,0x2
58: 00aa82b3 add t0,s5,a0
5c: 00aa0333 add t1,s4,a0
60: 00a983b3 add t2,s3,a0
64: 02092803 lw a6,32(s2)
68: 01c92e03 lw t3,28(s2)
6c: 00000893 li a7,0
70: 00000e93 li t4,0
74: 00028513 mv a0,t0
78: 00030593 mv a1,t1
7c: 00038613 mv a2,t2
80: 00000793 li a5,0
84: 00052703 lw a4,0(a0)
88: 0005a683 lw a3,0(a1)
8c: 00e686b3 add a3,a3,a4
90: 00d62023 sw a3,0(a2)
94: 00450513 addi a0,a0,4
98: 00458593 addi a1,a1,4
9c: 00460613 addi a2,a2,4
a0: 00178793 addi a5,a5,1
a4: fe97e0e3 bltu a5,s1,84 <_pocl_kernel_vecadd+0x84>
a8: 001e8e93 addi t4,t4,1
ac: fdcee4e3 bltu t4,t3,74 <_pocl_kernel_vecadd+0x74>
b0: 00188893 addi a7,a7,1
b4: fb08eee3 bltu a7,a6,70 <_pocl_kernel_vecadd+0x70>
b8: fe040113 addi sp,s0,-32
bc: 00412a83 lw s5,4(sp)
c0: 00812a03 lw s4,8(sp)
c4: 00c12983 lw s3,12(sp)
c8: 01012903 lw s2,16(sp)
cc: 01412483 lw s1,20(sp)
d0: 01812403 lw s0,24(sp)
d4: 01c12083 lw ra,28(sp)
d8: 02010113 addi sp,sp,32
dc: 00008067 ret
000000e0 <_pocl_kernel_vecadd_workgroup>:
e0: ff010113 addi sp,sp,-16
e4: 00112623 sw ra,12(sp)
e8: 00812423 sw s0,8(sp)
ec: 00912223 sw s1,4(sp)
f0: 01212023 sw s2,0(sp)
f4: 00058493 mv s1,a1
f8: 00050913 mv s2,a0
fc: 0185a403 lw s0,24(a1)
100: 00040513 mv a0,s0
104: 00060593 mv a1,a2
108: 00000097 auipc ra,0x0
10c: 000080e7 jalr ra # 108 <_pocl_kernel_vecadd_workgroup+0x28>
110: 00c4a583 lw a1,12(s1)
114: 00a58533 add a0,a1,a0
118: 00251513 slli a0,a0,0x2
11c: 00892583 lw a1,8(s2)
120: 0005a583 lw a1,0(a1)
124: 00492603 lw a2,4(s2)
128: 00062603 lw a2,0(a2)
12c: 00092683 lw a3,0(s2)
130: 0006a683 lw a3,0(a3)
134: 00a682b3 add t0,a3,a0
138: 00a60333 add t1,a2,a0
13c: 00a583b3 add t2,a1,a0
140: 0204a803 lw a6,32(s1)
144: 01c4ae03 lw t3,28(s1)
148: 00000893 li a7,0
14c: 00000493 li s1,0
150: 00028513 mv a0,t0
154: 00030593 mv a1,t1
158: 00038613 mv a2,t2
15c: 00000793 li a5,0
160: 00052683 lw a3,0(a0)
164: 0005a703 lw a4,0(a1)
168: 00d706b3 add a3,a4,a3
16c: 00d62023 sw a3,0(a2)
170: 00450513 addi a0,a0,4
174: 00458593 addi a1,a1,4
178: 00460613 addi a2,a2,4
17c: 00178793 addi a5,a5,1
180: fe87e0e3 bltu a5,s0,160 <_pocl_kernel_vecadd_workgroup+0x80>
184: 00148493 addi s1,s1,1
188: fdc4e4e3 bltu s1,t3,150 <_pocl_kernel_vecadd_workgroup+0x70>
18c: 00188893 addi a7,a7,1
190: fb08eee3 bltu a7,a6,14c <_pocl_kernel_vecadd_workgroup+0x6c>
194: 00012903 lw s2,0(sp)
198: 00412483 lw s1,4(sp)
19c: 00812403 lw s0,8(sp)
1a0: 00c12083 lw ra,12(sp)
1a4: 01010113 addi sp,sp,16
1a8: 00008067 ret
000001ac <_pocl_kernel_vecadd_workgroup_fast>:
1ac: ff010113 addi sp,sp,-16
1b0: 00112623 sw ra,12(sp)
1b4: 00812423 sw s0,8(sp)
1b8: 00912223 sw s1,4(sp)
1bc: 01212023 sw s2,0(sp)
1c0: 00058493 mv s1,a1
1c4: 00050913 mv s2,a0
1c8: 0185a403 lw s0,24(a1)
1cc: 00040513 mv a0,s0
1d0: 00060593 mv a1,a2
1d4: 00000097 auipc ra,0x0
1d8: 000080e7 jalr ra # 1d4 <_pocl_kernel_vecadd_workgroup_fast+0x28>
1dc: 00c4a583 lw a1,12(s1)
1e0: 00a58533 add a0,a1,a0
1e4: 00251513 slli a0,a0,0x2
1e8: 00892583 lw a1,8(s2)
1ec: 00492603 lw a2,4(s2)
1f0: 00092683 lw a3,0(s2)
1f4: 00a682b3 add t0,a3,a0
1f8: 00a60333 add t1,a2,a0
1fc: 00a583b3 add t2,a1,a0
200: 0204a803 lw a6,32(s1)
204: 01c4ae03 lw t3,28(s1)
208: 00000893 li a7,0
20c: 00000493 li s1,0
210: 00028513 mv a0,t0
214: 00030593 mv a1,t1
218: 00038613 mv a2,t2
21c: 00000793 li a5,0
220: 00052683 lw a3,0(a0)
224: 0005a703 lw a4,0(a1)
228: 00d706b3 add a3,a4,a3
22c: 00d62023 sw a3,0(a2)
230: 00450513 addi a0,a0,4
234: 00458593 addi a1,a1,4
238: 00460613 addi a2,a2,4
23c: 00178793 addi a5,a5,1
240: fe87e0e3 bltu a5,s0,220 <_pocl_kernel_vecadd_workgroup_fast+0x74>
244: 00148493 addi s1,s1,1
248: fdc4e4e3 bltu s1,t3,210 <_pocl_kernel_vecadd_workgroup_fast+0x64>
24c: 00188893 addi a7,a7,1
250: fb08eee3 bltu a7,a6,20c <_pocl_kernel_vecadd_workgroup_fast+0x60>
254: 00012903 lw s2,0(sp)
258: 00412483 lw s1,4(sp)
25c: 00812403 lw s0,8(sp)
260: 00c12083 lw ra,12(sp)
264: 01010113 addi sp,sp,16
268: 00008067 ret
Disassembly of section .comment:
00000000 <.comment>:
0: 6300 flw fs0,0(a4)
2: 616c flw fa1,68(a0)
4: 676e flw fa4,216(sp)
6: 7620 flw fs0,104(a2)
8: 7265 lui tp,0xffff9
a: 6e6f6973 csrrsi s2,0x6e6,30
e: 3920 fld fs0,112(a0)
10: 302e fld ft0,232(sp)
12: 312e fld ft2,232(sp)
14: 2820 fld fs0,80(s0)
16: 7468 flw fa0,108(s0)
18: 7074 flw fa3,100(s0)
1a: 2f2f3a73 csrrc s4,0x2f2,t5
1e: 68746967 0x68746967
22: 6275 lui tp,0x1d
24: 632e flw ft6,200(sp)
26: 6c2f6d6f jal s10,f66e8 <_pocl_kernel_vecadd_workgroup_fast+0xf653c>
2a: 766c flw fa1,108(a2)
2c: 2d6d jal 6e6 <_pocl_kernel_vecadd_workgroup_fast+0x53a>
2e: 696d lui s2,0x1b
30: 7272 flw ft4,60(sp)
32: 632f726f jal tp,f7664 <_pocl_kernel_vecadd_workgroup_fast+0xf74b8>
36: 616c flw fa1,68(a0)
38: 676e flw fa4,216(sp)
3a: 672e flw fa4,200(sp)
3c: 7469 lui s0,0xffffa
3e: 6220 flw fs0,64(a2)
40: 6465 lui s0,0x19
42: 34643733 0x34643733
46: 3162 fld ft2,56(sp)
48: 6338 flw fa4,64(a4)
4a: 3665 jal fffffbf2 <_pocl_kernel_vecadd_workgroup_fast+0xfffffa46>
4c: 3939 jal fffffc6a <_pocl_kernel_vecadd_workgroup_fast+0xfffffabe>
4e: 32636633 0x32636633
52: 3635 jal fffffb7e <_pocl_kernel_vecadd_workgroup_fast+0xfffff9d2>
54: 64386537 lui a0,0x64386
58: 3665 jal fffffc00 <_pocl_kernel_vecadd_workgroup_fast+0xfffffa54>
5a: 6631 lui a2,0xc
5c: 6236 flw ft4,76(sp)
5e: 64663033 0x64663033
62: 6330 flw fa2,64(a4)
64: 3762 fld fa4,56(sp)
66: 2935 jal 4a2 <_pocl_kernel_vecadd_workgroup_fast+0x2f6>
68: 2820 fld fs0,80(s0)
6a: 7468 flw fa0,108(s0)
6c: 7074 flw fa3,100(s0)
6e: 2f2f3a73 csrrc s4,0x2f2,t5
72: 68746967 0x68746967
76: 6275 lui tp,0x1d
78: 632e flw ft6,200(sp)
7a: 6c2f6d6f jal s10,f673c <_pocl_kernel_vecadd_workgroup_fast+0xf6590>
7e: 766c flw fa1,108(a2)
80: 2d6d jal 73a <_pocl_kernel_vecadd_workgroup_fast+0x58e>
82: 696d lui s2,0x1b
84: 7272 flw ft4,60(sp)
86: 6c2f726f jal tp,f7748 <_pocl_kernel_vecadd_workgroup_fast+0xf759c>
8a: 766c flw fa1,108(a2)
8c: 2e6d jal 446 <_pocl_kernel_vecadd_workgroup_fast+0x29a>
8e: 20746967 0x20746967
92: 35663263 0x35663263
96: 62393033 0x62393033
9a: 3132 fld ft2,296(sp)
9c: 6336 flw ft6,76(sp)
9e: 3062 fld ft0,56(sp)
a0: 6132 flw ft2,12(sp)
a2: 6130 flw fa2,64(a0)
a4: 6561 lui a0,0x18
a6: 3731 jal ffffffb2 <_pocl_kernel_vecadd_workgroup_fast+0xfffffe06>
a8: 35333533 0x35333533
ac: 3934 fld fa3,112(a0)
ae: 3964 fld fs1,240(a0)
b0: 3538 fld fa4,104(a0)
b2: 3562 fld fa0,56(sp)
b4: 3062 fld ft0,56(sp)
b6: 3635 jal fffffbe2 <_pocl_kernel_vecadd_workgroup_fast+0xfffffa36>
b8: 00293533 sltu a0,s2,sp

BIN
runtime/mains/vecadd/libs/vecadd
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494132
runtime/mains/vecadd/libs/vecadd.dump
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490342
runtime/mains/vecadd/vx_pocl_main.dump
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BIN
runtime/mains/vecadd/vx_pocl_main.elf
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21589
runtime/mains/vecadd/vx_pocl_main.hex
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3
runtime/mains/vector_test/Makefile
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@ -36,3 +36,6 @@ HEX: ELF
ELF:
$(COMP) $(CC_FLAGS) $(VX_STR) $(VX_VEC) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_TEST) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf
clean:
rm -rf *.o *.elf *.dump *.hex *.qemu *.log *.debug

11500
runtime/mains/vector_test/vx_vector_main.dump
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runtime/mains/vector_test/vx_vector_main.elf
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592
runtime/mains/vector_test/vx_vector_main.hex
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@ -1,592 +0,0 @@
:0200000480007A
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:10001000EF004005130510006B0005001385C108B3
:100020001386810C3306A64093050000EF10403C78
:1000300017150000130505AFEF00502AEF005034EC
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3
rvvector/benchmark_temp/Makefile
View file

@ -38,3 +38,6 @@ ELF:
# $(COMP) $(CC_FLAGS) $(VX_STR) $(VX_VEC3) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_TEST) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf
# $(COMP) $(CC_FLAGS) $(VX_STR) $(VX_VEC4) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_TEST) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf
# $(COMP) $(CC_FLAGS) $(VX_STR) $(VX_VEC5) $(VX_FIO) $(NEWLIB) $(VX_INT) $(VX_IO) $(VX_API) $(VX_TEST) $(VX_MAIN).c $(LIBS) -Iinclude -o $(VX_MAIN).elf~
clean:
rm -rf *.o *.elf *.dump *.hex *.qemu *.log *.debug

87070
rvvector/benchmark_temp/vx_vec_benchmark.dump
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rvvector/benchmark_temp/vx_vec_benchmark.elf
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5595
rvvector/benchmark_temp/vx_vec_benchmark.hex
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simX/obj_dir/Vcache_simX
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4256
simX/obj_dir/Vcache_simX.cpp
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321
simX/obj_dir/Vcache_simX.h
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@ -1,321 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef _Vcache_simX_H_
#define _Vcache_simX_H_
#include "verilated.h"
class Vcache_simX__Syms;
class Vcache_simX_VX_dram_req_rsp_inter__N4_NB4;
class Vcache_simX_VX_dcache_request_inter;
class Vcache_simX_VX_Cache_Bank__pi8;
class Vcache_simX_VX_Cache_Bank__pi9;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX) {
public:
// CELLS
// Public to allow access to /*verilator_public*/ items;
// otherwise the application code can consider these internals.
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4* __PVT__cache_simX__DOT__VX_dram_req_rsp_icache;
Vcache_simX_VX_dcache_request_inter* __PVT__cache_simX__DOT__VX_dcache_req;
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4* __PVT__cache_simX__DOT__VX_dram_req_rsp;
Vcache_simX_VX_Cache_Bank__pi8* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi8* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi8* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi8* __PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi9* __PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi9* __PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi9* __PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi9* __PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
VL_IN8(clk,0,0);
VL_IN8(reset,0,0);
VL_IN8(in_icache_valid_pc_addr,0,0);
VL_OUT8(out_icache_stall,0,0);
VL_IN8(in_dcache_mem_read,2,0);
VL_IN8(in_dcache_mem_write,2,0);
VL_OUT8(out_dcache_stall,0,0);
VL_IN(in_icache_pc_addr,31,0);
VL_IN8(in_dcache_in_valid[4],0,0);
VL_IN(in_dcache_in_address[4],31,0);
// LOCAL SIGNALS
// Internals; generally not touched by application code
VL_SIG8(cache_simX__DOT__icache_i_m_ready,0,0);
VL_SIG8(cache_simX__DOT__dcache_i_m_ready,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__sm_driver_in_valid,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__cache_driver_in_valid,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__read_or_write,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_read,2,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__cache_driver_in_mem_write,2,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_read,2,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__sm_driver_in_mem_write,2,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache_driver_in_mem_read,2,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_valid,3,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr,27,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_we,7,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__orig_in_valid,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__shm_write,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__shm_write,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__shm_write,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__shm_write,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__left_requests,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__use_valid,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_req_num,7,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__internal_out_valid,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__serviced_qual,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__new_left_requests,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__0__KET____DOT__num_valids,2,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__1__KET____DOT__num_valids,2,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__2__KET____DOT__num_valids,2,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk1__BRA__3__KET____DOT__num_valids,2,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__global_way_to_evict,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__index_per_bank,7,0);
VL_SIG16(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_mask_per_bank,15,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__valid_per_bank,3,0);
VL_SIG16(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_per_bank,15,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__hit_per_bank,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_wb_old,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__state,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_state,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__use_valid,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__stored_valid,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_stored_valid,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__threads_serviced_Qual,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__detect_bank_miss,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__update_global_way_to_evict,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__global_way_to_evict,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__index_per_bank,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_mask_per_bank,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__valid_per_bank,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_per_bank,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__hit_per_bank,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_wb_old,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__state,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_state,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__use_valid,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__stored_valid,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_stored_valid,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__threads_serviced_Qual,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__detect_bank_miss,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__update_global_way_to_evict,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__use_valid_in,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__use_valid_in,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__use_valid_in,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__use_valid_in,0,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__temp_out_data,127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_wdata,511,0,16);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_rdata,511,0,16);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__curr_ind,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__curr_ind,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__curr_ind,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__curr_ind,31,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__final_data_read,127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read,127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__new_final_data_read_Qual,127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__readdata_per_bank,127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__eviction_addr_per_bank,127,0,4);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__init_b,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__final_data_read,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__new_final_data_read_Qual,31,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__readdata_per_bank,127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__icache__DOT__eviction_addr_per_bank,127,0,4);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__init_b,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_addr,31,0);
VL_SIG(cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i,31,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__0__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__1__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__2__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__genblk2__BRA__3__KET____DOT__vx_shared_memory_block__DOT__shared_memory[128],127,0,4);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__debug_hit_per_bank_mask[4],3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__debug_hit_per_bank_mask[4],0,0);
// LOCAL VARIABLES
// Internals; generally not touched by application code
static VL_ST_SIG8(__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index[16],1,0);
static VL_ST_SIG8(__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found[16],0,0);
static VL_ST_SIG(__Vtable1_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT__vx_priority_encoder__DOT__i[16],31,0);
static VL_ST_SIG8(__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index[16],1,0);
static VL_ST_SIG8(__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found[16],0,0);
static VL_ST_SIG(__Vtable2_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT__vx_priority_encoder__DOT__i[16],31,0);
static VL_ST_SIG8(__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index[16],1,0);
static VL_ST_SIG8(__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found[16],0,0);
static VL_ST_SIG(__Vtable3_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT__vx_priority_encoder__DOT__i[16],31,0);
static VL_ST_SIG8(__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index[16],1,0);
static VL_ST_SIG8(__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found[16],0,0);
static VL_ST_SIG(__Vtable4_cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT__vx_priority_encoder__DOT__i[16],31,0);
static VL_ST_SIG8(__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_bank_index[16],1,0);
static VL_ST_SIG8(__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__miss_found[16],0,0);
static VL_ST_SIG(__Vtable5_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__get_miss_index__DOT__i[16],31,0);
static VL_ST_SIG8(__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index[16],1,0);
static VL_ST_SIG8(__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found[16],0,0);
static VL_ST_SIG(__Vtable6_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT__choose_thread__DOT__i[16],31,0);
static VL_ST_SIG8(__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index[16],1,0);
static VL_ST_SIG8(__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found[16],0,0);
static VL_ST_SIG(__Vtable7_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT__choose_thread__DOT__i[16],31,0);
static VL_ST_SIG8(__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index[16],1,0);
static VL_ST_SIG8(__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found[16],0,0);
static VL_ST_SIG(__Vtable8_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT__choose_thread__DOT__i[16],31,0);
static VL_ST_SIG8(__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index[16],1,0);
static VL_ST_SIG8(__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found[16],0,0);
static VL_ST_SIG(__Vtable9_cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT__choose_thread__DOT__i[16],31,0);
static VL_ST_SIG8(__Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_bank_index[16],1,0);
static VL_ST_SIG8(__Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__miss_found[16],0,0);
static VL_ST_SIG(__Vtable10_cache_simX__DOT__dmem_controller__DOT__icache__DOT__get_miss_index__DOT__i[16],31,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound1,6,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vlvbound2,6,0);
VL_SIG16(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT____Vcellout__vx_bank_valid__bank_valids,15,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__0__KET____DOT____Vcellout__vx_priority_encoder__index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__1__KET____DOT____Vcellout__vx_priority_encoder__index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__2__KET____DOT____Vcellout__vx_priority_encoder__index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__vx_priority_encoder_sm__DOT__genblk2__BRA__3__KET____DOT____Vcellout__vx_priority_encoder__index,1,0);
VL_SIG16(cache_simX__DOT__dmem_controller__DOT__dcache__DOT____Vcellout__multip_banks__thread_track_banks,15,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index,1,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT____Vcellout__multip_banks__thread_track_banks,3,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__0__KET____DOT____Vcellout__choose_thread__index,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__1__KET____DOT____Vcellout__choose_thread__index,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__2__KET____DOT____Vcellout__choose_thread__index,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__found,0,0);
VL_SIG8(cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk1__BRA__3__KET____DOT____Vcellout__choose_thread__index,0,0);
VL_SIG8(__Vtableidx1,3,0);
VL_SIG8(__Vtableidx2,3,0);
VL_SIG8(__Vtableidx3,3,0);
VL_SIG8(__Vtableidx4,3,0);
VL_SIG8(__Vtableidx5,3,0);
VL_SIG8(__Vtableidx6,3,0);
VL_SIG8(__Vtableidx7,3,0);
VL_SIG8(__Vtableidx8,3,0);
VL_SIG8(__Vtableidx9,3,0);
VL_SIG8(__Vtableidx10,3,0);
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG(__Vchglast__TOP__cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT__block_addr,27,0);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT____Vcellout__dcache__o_m_writedata,511,0,16);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT____Vcellout__icache__o_m_writedata,511,0,16);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_data,127,0,4);
VL_SIGW(cache_simX__DOT__dmem_controller__DOT__shared_memory__DOT____Vcellout__vx_priority_encoder_sm__out_address,127,0,4);
VL_SIG(__Vm_traceActivity,31,0);
// INTERNAL VARIABLES
// Internals; generally not touched by application code
Vcache_simX__Syms* __VlSymsp; // Symbol table
// PARAMETERS
// Parameters marked /*verilator public*/ for use by application code
// CONSTRUCTORS
private:
Vcache_simX& operator= (const Vcache_simX&); ///< Copying not allowed
Vcache_simX(const Vcache_simX&); ///< Copying not allowed
public:
/// Construct the model; called by application code
/// The special name may be used to make a wrapper with a
/// single model invisible WRT DPI scope names.
Vcache_simX(const char* name="TOP");
/// Destroy the model; called (often implicitly) by application code
~Vcache_simX();
/// Trace signals in the model; called by application code
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval();
/// Simulation complete, run final blocks. Application must call on completion.
void final();
// INTERNAL METHODS
private:
static void _eval_initial_loop(Vcache_simX__Syms* __restrict vlSymsp);
public:
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
private:
static QData _change_request(Vcache_simX__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__1(Vcache_simX__Syms* __restrict vlSymsp);
static void _combo__TOP__5(Vcache_simX__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset();
public:
static void _eval(Vcache_simX__Syms* __restrict vlSymsp);
private:
#ifdef VL_DEBUG
void _eval_debug_assertions();
#endif // VL_DEBUG
public:
static void _eval_initial(Vcache_simX__Syms* __restrict vlSymsp);
static void _eval_settle(Vcache_simX__Syms* __restrict vlSymsp);
static void _sequent__TOP__4(Vcache_simX__Syms* __restrict vlSymsp);
static void _settle__TOP__2(Vcache_simX__Syms* __restrict vlSymsp);
static void _settle__TOP__3(Vcache_simX__Syms* __restrict vlSymsp);
static void traceChgThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__3(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__4(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__5(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__6(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceFullThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceInitThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceInitThis__1(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif // guard

85
simX/obj_dir/Vcache_simX.mk
View file

@ -1,85 +0,0 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f Vcache_simX.mk
default: Vcache_simX
### Constants...
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?= /opt/systemc/include
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?= /opt/systemc/lib
### Switches...
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC)
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = Vcache_simX
# Module prefix (from --prefix)
VM_MODPREFIX = Vcache_simX
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
-std=c++11 -fPIC -O3 -Wall -Wextra -pedantic \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
args \
core \
enc \
instruction \
mem \
simX \
util \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
. \
### Default rules...
# Include list of all generated classes
include Vcache_simX_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
### Executable rules... (from --exe)
VPATH += $(VM_USER_DIR)
args.o: args.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
core.o: core.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
enc.o: enc.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
instruction.o: instruction.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
mem.o: mem.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
simX.o: simX.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
util.o: util.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
### Link rules... (from --exe)
Vcache_simX: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS) 2>&1 | c++filt
# Verilated -*- Makefile -*-

8519
simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp
View file

File diff suppressed because it is too large Load diff

272
simX/obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h
View file

@ -1,272 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_Cache_Bank__pi8_H_
#define _Vcache_simX_VX_Cache_Bank__pi8_H_
#include "verilated.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_Cache_Bank__pi8) {
public:
// PORTS
VL_IN8(rst,0,0);
VL_IN8(clk,0,0);
VL_IN8(state,3,0);
VL_IN8(actual_index,4,0);
VL_IN8(block_offset,1,0);
VL_IN8(valid_in,0,0);
VL_IN8(read_or_write,0,0);
VL_IN8(i_p_mem_read,2,0);
VL_IN8(i_p_mem_write,2,0);
VL_IN8(byte_select,1,0);
VL_IN8(evicted_way,0,0);
VL_OUT8(hit,0,0);
VL_OUT8(eviction_wb,0,0);
VL_IN(o_tag,20,0);
VL_IN(writedata,31,0);
VL_INW(fetched_writedata,127,0,4);
VL_OUT(readdata,31,0);
VL_OUT(eviction_addr,31,0);
VL_OUTW(data_evicted,127,0,4);
// LOCAL SIGNALS
VL_SIG8(__PVT__valid_use,0,0);
VL_SIG8(__PVT__access,0,0);
VL_SIG8(__PVT__write_from_mem,0,0);
VL_SIG8(__PVT__miss,0,0);
VL_SIG8(__PVT__way_to_update,0,0);
VL_SIG8(__PVT__sb_mask,3,0);
VL_SIG16(__PVT__we,15,0);
VL_SIG8(__PVT__genblk1__BRA__0__KET____DOT__normal_write,0,0);
VL_SIG8(__PVT__genblk1__BRA__1__KET____DOT__normal_write,0,0);
VL_SIG8(__PVT__genblk1__BRA__2__KET____DOT__normal_write,0,0);
VL_SIG8(__PVT__genblk1__BRA__3__KET____DOT__normal_write,0,0);
VL_SIG8(__PVT__data_structures__DOT__valid_use_per_way,1,0);
VL_SIG8(__PVT__data_structures__DOT__dirty_use_per_way,1,0);
VL_SIG8(__PVT__data_structures__DOT__hit_per_way,1,0);
VL_SIG(__PVT__data_structures__DOT__we_per_way,31,0);
VL_SIG8(__PVT__data_structures__DOT__write_from_mem_per_way,1,0);
VL_SIG8(__PVT__data_structures__DOT__invalid_found,0,0);
VL_SIG8(__PVT__data_structures__DOT__way_index,0,0);
VL_SIG8(__PVT__data_structures__DOT__invalid_index,0,0);
VL_SIG8(__PVT__data_structures__DOT__way_use_Qual,0,0);
VL_SIG8(__PVT__data_structures__DOT__genblk1__DOT__way_indexing__DOT__found,0,0);
VL_SIG(__PVT__tag_use,20,0);
VL_SIG(__PVT__data_unQual,31,0);
VL_SIG(__PVT__use_write_data,31,0);
VL_SIGW(__PVT__data_write,127,0,4);
VL_SIG64(__PVT__data_structures__DOT__tag_use_per_way,41,0);
VL_SIGW(__PVT__data_structures__DOT__data_use_per_way,255,0,8);
VL_SIGW(__PVT__data_structures__DOT__data_write_per_way,255,0,8);
VL_SIG(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__f,31,0);
VL_SIG(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__ini_ind,31,0);
VL_SIG(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__f,31,0);
VL_SIG(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__ini_ind,31,0);
VL_SIGW(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data[32],127,0,4);
VL_SIG(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag[32],20,0);
VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid[32],0,0);
VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty[32],0,0);
VL_SIGW(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data[32],127,0,4);
VL_SIG(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag[32],20,0);
VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid[32],0,0);
VL_SIG8(__PVT__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty[32],0,0);
// LOCAL VARIABLES
VL_SIG8(data_structures__DOT__each_way__BRA__0__KET____DOT____Vcellout__data_structures__dirty_use,0,0);
VL_SIG8(data_structures__DOT__each_way__BRA__1__KET____DOT____Vcellout__data_structures__dirty_use,0,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v0,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32,4,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32,0,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__dirty__v32,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32,4,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32,4,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__valid__v32,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v32,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v33,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v34,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v35,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v36,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v37,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v38,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v39,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v40,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v41,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v42,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v43,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v44,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v45,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v46,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__data__v47,0,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v0,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32,4,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32,0,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__dirty__v32,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32,4,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32,4,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__valid__v32,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v32,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v33,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v34,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v35,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v36,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v37,7,0);
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VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v38,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v39,7,0);
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VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v42,0,0);
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VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v43,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v44,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v45,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v46,0,0);
VL_SIG8(__Vdlyvdim0__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47,4,0);
VL_SIG8(__Vdlyvlsb__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47,6,0);
VL_SIG8(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47,7,0);
VL_SIG8(__Vdlyvset__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__data__v47,0,0);
VL_SIGW(__Vcellout__data_structures__data_use,127,0,4);
VL_SIG(__Vdlyvval__data_structures__DOT__each_way__BRA__0__KET____DOT__data_structures__DOT__tag__v32,20,0);
VL_SIG(__Vdlyvval__data_structures__DOT__each_way__BRA__1__KET____DOT__data_structures__DOT__tag__v32,20,0);
// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_Cache_Bank__pi8& operator= (const Vcache_simX_VX_Cache_Bank__pi8&); ///< Copying not allowed
Vcache_simX_VX_Cache_Bank__pi8(const Vcache_simX_VX_Cache_Bank__pi8&); ///< Copying not allowed
public:
Vcache_simX_VX_Cache_Bank__pi8(const char* name="TOP");
~Vcache_simX_VX_Cache_Bank__pi8();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
void _combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__9(Vcache_simX__Syms* __restrict vlSymsp);
void _combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__10(Vcache_simX__Syms* __restrict vlSymsp);
void _combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__11(Vcache_simX__Syms* __restrict vlSymsp);
void _combo__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__12(Vcache_simX__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset();
public:
void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__5(Vcache_simX__Syms* __restrict vlSymsp);
void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__6(Vcache_simX__Syms* __restrict vlSymsp);
void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__7(Vcache_simX__Syms* __restrict vlSymsp);
void _sequent__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__8(Vcache_simX__Syms* __restrict vlSymsp);
void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure__1(Vcache_simX__Syms* __restrict vlSymsp);
void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure__2(Vcache_simX__Syms* __restrict vlSymsp);
void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure__3(Vcache_simX__Syms* __restrict vlSymsp);
void _settle__TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure__4(Vcache_simX__Syms* __restrict vlSymsp);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif // guard

37
simX/obj_dir/Vcache_simX_VX_dcache_request_inter.cpp
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@ -1,37 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_dcache_request_inter.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_dcache_request_inter) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void Vcache_simX_VX_dcache_request_inter::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_dcache_request_inter::~Vcache_simX_VX_dcache_request_inter() {
}
//--------------------
// Internal Methods
void Vcache_simX_VX_dcache_request_inter::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_dcache_request_inter::_ctor_var_reset\n"); );
// Body
VL_RAND_RESET_W(128,out_cache_driver_in_address);
out_cache_driver_in_valid = VL_RAND_RESET_I(4);
}

54
simX/obj_dir/Vcache_simX_VX_dcache_request_inter.h
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@ -1,54 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_dcache_request_inter_H_
#define _Vcache_simX_VX_dcache_request_inter_H_
#include "verilated.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_dcache_request_inter) {
public:
// PORTS
// LOCAL SIGNALS
VL_SIG8(out_cache_driver_in_valid,3,0);
VL_SIGW(out_cache_driver_in_address,127,0,4);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_dcache_request_inter& operator= (const Vcache_simX_VX_dcache_request_inter&); ///< Copying not allowed
Vcache_simX_VX_dcache_request_inter(const Vcache_simX_VX_dcache_request_inter&); ///< Copying not allowed
public:
Vcache_simX_VX_dcache_request_inter(const char* name="TOP");
~Vcache_simX_VX_dcache_request_inter();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
private:
void _ctor_var_reset();
public:
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif // guard

36
simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp
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@ -1,36 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_dram_req_rsp_inter__N4_NB4) {
// Reset internal values
// Reset structure values
_ctor_var_reset();
}
void Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::~Vcache_simX_VX_dram_req_rsp_inter__N4_NB4() {
}
//--------------------
// Internal Methods
void Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::_ctor_var_reset() {
VL_DEBUG_IF(VL_DBG_MSGF("+ Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::_ctor_var_reset\n"); );
// Body
VL_RAND_RESET_W(512,i_m_readdata);
}

53
simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h
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@ -1,53 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_dram_req_rsp_inter__N4_NB4_H_
#define _Vcache_simX_VX_dram_req_rsp_inter__N4_NB4_H_
#include "verilated.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_dram_req_rsp_inter__N4_NB4) {
public:
// PORTS
// LOCAL SIGNALS
VL_SIGW(i_m_readdata,511,0,16);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4& operator= (const Vcache_simX_VX_dram_req_rsp_inter__N4_NB4&); ///< Copying not allowed
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4(const Vcache_simX_VX_dram_req_rsp_inter__N4_NB4&); ///< Copying not allowed
public:
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4(const char* name="TOP");
~Vcache_simX_VX_dram_req_rsp_inter__N4_NB4();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
private:
void _ctor_var_reset();
public:
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif // guard

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simX/obj_dir/Vcache_simX__ALL.a
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simX/obj_dir/Vcache_simX__ALLcls.cpp
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@ -1,7 +0,0 @@
// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "Vcache_simX.cpp"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
#include "Vcache_simX_VX_dcache_request_inter.cpp"
#include "Vcache_simX_VX_Cache_Bank__pi9.cpp"
#include "Vcache_simX_VX_Cache_Bank__pi8.cpp"

10
simX/obj_dir/Vcache_simX__ALLcls.d
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@ -1,10 +0,0 @@
Vcache_simX__ALLcls.o: Vcache_simX__ALLcls.cpp Vcache_simX.cpp \
Vcache_simX.h /usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h Vcache_simX__Syms.h \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h \
Vcache_simX_VX_dcache_request_inter.h Vcache_simX_VX_Cache_Bank__pi9.h \
Vcache_simX_VX_Cache_Bank__pi8.h \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp \
Vcache_simX_VX_dcache_request_inter.cpp \
Vcache_simX_VX_Cache_Bank__pi9.cpp Vcache_simX_VX_Cache_Bank__pi8.cpp

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5
simX/obj_dir/Vcache_simX__ALLsup.cpp
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@ -1,5 +0,0 @@
// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "Vcache_simX__Trace.cpp"
#include "Vcache_simX__Syms.cpp"
#include "Vcache_simX__Trace__Slow.cpp"

10
simX/obj_dir/Vcache_simX__ALLsup.d
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@ -1,10 +0,0 @@
Vcache_simX__ALLsup.o: Vcache_simX__ALLsup.cpp Vcache_simX__Trace.cpp \
/usr/share/verilator/include/verilated_vcd_c.h \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h Vcache_simX__Syms.h \
/usr/share/verilator/include/verilated.h Vcache_simX.h \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h \
Vcache_simX_VX_dcache_request_inter.h Vcache_simX_VX_Cache_Bank__pi9.h \
Vcache_simX_VX_Cache_Bank__pi8.h Vcache_simX__Syms.cpp \
Vcache_simX__Trace__Slow.cpp

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57
simX/obj_dir/Vcache_simX__Syms.cpp
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@ -1,57 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "Vcache_simX__Syms.h"
#include "Vcache_simX.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
#include "Vcache_simX_VX_dcache_request_inter.h"
#include "Vcache_simX_VX_Cache_Bank__pi9.h"
#include "Vcache_simX_VX_Cache_Bank__pi8.h"
// FUNCTIONS
Vcache_simX__Syms::Vcache_simX__Syms(Vcache_simX* topp, const char* namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_activity(false)
, __Vm_didInit(false)
// Setup submodule names
, TOP__cache_simX__DOT__VX_dcache_req (Verilated::catName(topp->name(),"cache_simX.VX_dcache_req"))
, TOP__cache_simX__DOT__VX_dram_req_rsp (Verilated::catName(topp->name(),"cache_simX.VX_dram_req_rsp"))
, TOP__cache_simX__DOT__VX_dram_req_rsp_icache (Verilated::catName(topp->name(),"cache_simX.VX_dram_req_rsp_icache"))
, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[0].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[1].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[2].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[3].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.icache.genblk3[0].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.icache.genblk3[1].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.icache.genblk3[2].bank_structure"))
, TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.icache.genblk3[3].bank_structure"))
{
// Pointer to top level
TOPp = topp;
// Setup each module's pointers to their submodules
TOPp->__PVT__cache_simX__DOT__VX_dcache_req = &TOP__cache_simX__DOT__VX_dcache_req;
TOPp->__PVT__cache_simX__DOT__VX_dram_req_rsp = &TOP__cache_simX__DOT__VX_dram_req_rsp;
TOPp->__PVT__cache_simX__DOT__VX_dram_req_rsp_icache = &TOP__cache_simX__DOT__VX_dram_req_rsp_icache;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
TOP__cache_simX__DOT__VX_dcache_req.__Vconfigure(this, true);
TOP__cache_simX__DOT__VX_dram_req_rsp.__Vconfigure(this, true);
TOP__cache_simX__DOT__VX_dram_req_rsp_icache.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vconfigure(this, true);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vconfigure(this, true);
TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vconfigure(this, false);
TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vconfigure(this, false);
}

51
simX/obj_dir/Vcache_simX__Syms.h
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@ -1,51 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header
#ifndef _Vcache_simX__Syms_H_
#define _Vcache_simX__Syms_H_
#include "verilated.h"
// INCLUDE MODULE CLASSES
#include "Vcache_simX.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
#include "Vcache_simX_VX_dcache_request_inter.h"
#include "Vcache_simX_VX_Cache_Bank__pi9.h"
#include "Vcache_simX_VX_Cache_Bank__pi8.h"
// SYMS CLASS
class Vcache_simX__Syms : public VerilatedSyms {
public:
// LOCAL STATE
const char* __Vm_namep;
bool __Vm_activity; ///< Used by trace routines to determine change occurred
bool __Vm_didInit;
// SUBCELL STATE
Vcache_simX* TOPp;
Vcache_simX_VX_dcache_request_inter TOP__cache_simX__DOT__VX_dcache_req;
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 TOP__cache_simX__DOT__VX_dram_req_rsp;
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 TOP__cache_simX__DOT__VX_dram_req_rsp_icache;
Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi8 TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi9 TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi9 TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi9 TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
Vcache_simX_VX_Cache_Bank__pi9 TOP__cache_simX__DOT__dmem_controller__DOT__icache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
// CREATORS
Vcache_simX__Syms(Vcache_simX* topp, const char* namep);
~Vcache_simX__Syms() {}
// METHODS
inline const char* name() { return __Vm_namep; }
inline bool getClearActivity() { bool r=__Vm_activity; __Vm_activity=false; return r; }
} VL_ATTR_ALIGNED(64);
#endif // guard

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simX/obj_dir/Vcache_simX__Trace.cpp
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simX/obj_dir/Vcache_simX__Trace__Slow.cpp
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simX/obj_dir/Vcache_simX__ver.d
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obj_dir/Vcache_simX.cpp obj_dir/Vcache_simX.h obj_dir/Vcache_simX.mk obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h obj_dir/Vcache_simX_VX_Cache_Bank__pi9.cpp obj_dir/Vcache_simX_VX_Cache_Bank__pi9.h obj_dir/Vcache_simX_VX_dcache_request_inter.cpp obj_dir/Vcache_simX_VX_dcache_request_inter.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h obj_dir/Vcache_simX__Syms.cpp obj_dir/Vcache_simX__Syms.h obj_dir/Vcache_simX__Trace.cpp obj_dir/Vcache_simX__Trace__Slow.cpp obj_dir/Vcache_simX__ver.d obj_dir/Vcache_simX_classes.mk : /usr/bin/verilator_bin ../rtl/./VX_define_synth.v ../rtl/VX_countones.v ../rtl/VX_define.v ../rtl/VX_dmem_controller.v ../rtl/VX_generic_priority_encoder.v ../rtl/VX_priority_encoder_w_mask.v ../rtl/cache/VX_Cache_Bank.v ../rtl/cache/VX_cache_bank_valid.v ../rtl/cache/VX_cache_data.v ../rtl/cache/VX_cache_data_per_index.v ../rtl/cache/VX_d_cache.v ../rtl/interfaces/VX_dcache_request_inter.v ../rtl/interfaces/VX_dcache_response_inter.v ../rtl/interfaces/VX_dram_req_rsp_inter.v ../rtl/interfaces/VX_icache_request_inter.v ../rtl/interfaces/VX_icache_response_inter.v ../rtl/shared_memory/../VX_define.v ../rtl/shared_memory/VX_bank_valids.v ../rtl/shared_memory/VX_priority_encoder_sm.v ../rtl/shared_memory/VX_shared_memory.v ../rtl/shared_memory/VX_shared_memory_block.v /usr/bin/verilator_bin cache_simX.v

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simX/obj_dir/Vcache_simX__verFiles.dat
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# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "--compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS -std=c++11 -fPIC -O3 -Wall -Wextra -pedantic -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1"
S 26 1407374883678355 1576858113 365285900 1576858113 365285900 "../rtl/./VX_define_synth.v"
S 283 1407374883678346 1576858113 363291200 1576858113 363291200 "../rtl/VX_countones.v"
S 7257 5629499534267235 1583028100 893817800 1583028100 893817800 "../rtl/VX_define.v"
S 8325 1407374883678357 1576858113 366283200 1576858113 366283200 "../rtl/VX_dmem_controller.v"
S 517 1407374883678365 1576858113 368277800 1576858113 368277800 "../rtl/VX_generic_priority_encoder.v"
S 683 1407374883678386 1576858113 374262300 1576858113 374262300 "../rtl/VX_priority_encoder_w_mask.v"
S 8590 1407374883678402 1576858113 378252100 1576858113 378252100 "../rtl/cache/VX_Cache_Bank.v"
S 748 1407374883678406 1576858113 379248400 1576858113 379248400 "../rtl/cache/VX_cache_bank_valid.v"
S 7349 1407374883678408 1576858113 380246000 1576858113 380246000 "../rtl/cache/VX_cache_data.v"
S 6476 1407374883678409 1576858113 380246000 1576858113 380246000 "../rtl/cache/VX_cache_data_per_index.v"
S 14645 1407374883678410 1576858113 381243100 1576858113 381243100 "../rtl/cache/VX_d_cache.v"
S 393 1407374883678432 1576858113 386229700 1576858113 386229700 "../rtl/interfaces/VX_dcache_request_inter.v"
S 215 1407374883678434 1576858113 387227400 1576858113 387227400 "../rtl/interfaces/VX_dcache_response_inter.v"
S 870 1407374883678435 1576858113 387227400 1576858113 387227400 "../rtl/interfaces/VX_dram_req_rsp_inter.v"
S 354 1407374883678447 1576858113 392213800 1576858113 392213800 "../rtl/interfaces/VX_icache_request_inter.v"
S 212 1407374883678448 1576858113 392213800 1576858113 392213800 "../rtl/interfaces/VX_icache_response_inter.v"
S 7257 5629499534267235 1583028100 893817800 1583028100 893817800 "../rtl/shared_memory/../VX_define.v"
S 676 1407374883678497 1576858113 417147000 1576858113 417147000 "../rtl/shared_memory/VX_bank_valids.v"
S 3038 1407374883678498 1576858113 418144200 1576858113 418144200 "../rtl/shared_memory/VX_priority_encoder_sm.v"
S 4962 1407374883678499 1576858113 418144200 1576858113 418144200 "../rtl/shared_memory/VX_shared_memory.v"
S 3207 1407374883678500 1576858113 419141900 1576858113 419141900 "../rtl/shared_memory/VX_shared_memory_block.v"
S 5279832 1125899907857040 1579658333 790142700 1519110675 0 "/usr/bin/verilator_bin"
S 3144 1407374883678789 1576858114 576047000 1576858114 576047000 "cache_simX.v"
T 390173 22236523160217637 1583612769 755410900 1583612769 755410900 "obj_dir/Vcache_simX.cpp"
T 28278 15481123719153127 1583612769 748398500 1583612769 748398500 "obj_dir/Vcache_simX.h"
T 2365 10133099161813405 1583612769 784337500 1583612769 784337500 "obj_dir/Vcache_simX.mk"
T 643931 3940649674155161 1583612769 783340900 1583612769 783340900 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.cpp"
T 23659 5348024557708078 1583612769 771372900 1583612769 771372900 "obj_dir/Vcache_simX_VX_Cache_Bank__pi8.h"
T 578414 15481123719285399 1583612769 770399200 1583612769 770399200 "obj_dir/Vcache_simX_VX_Cache_Bank__pi9.cpp"
T 23321 11258999068615501 1583612769 760411300 1583612769 760411300 "obj_dir/Vcache_simX_VX_Cache_Bank__pi9.h"
T 1024 8725724278219266 1583612769 757374600 1583612769 757374600 "obj_dir/Vcache_simX_VX_dcache_request_inter.cpp"
T 1561 50102545854682183 1583612769 757374600 1583612769 757374600 "obj_dir/Vcache_simX_VX_dcache_request_inter.h"
T 999 10414574138447661 1583612769 756377900 1583612769 756377900 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
T 1557 6755399441176779 1583612769 756377900 1583612769 756377900 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
T 6004 11821949021903061 1583612769 706686400 1583612769 706686400 "obj_dir/Vcache_simX__Syms.cpp"
T 2455 32088147345022597 1583612769 705722700 1583612769 705722700 "obj_dir/Vcache_simX__Syms.h"
T 1114242 10414574138355386 1583612769 747434700 1583612769 747434700 "obj_dir/Vcache_simX__Trace.cpp"
T 1433229 12103423998619303 1583612769 729412200 1583612769 729412200 "obj_dir/Vcache_simX__Trace__Slow.cpp"
T 1439 6755399441290555 1583612769 784337500 1583612769 784337500 "obj_dir/Vcache_simX__ver.d"
T 0 0 1583612769 844870300 1583612769 844870300 "obj_dir/Vcache_simX__verFiles.dat"
T 1392 4785074604292692 1583612769 784337500 1583612769 784337500 "obj_dir/Vcache_simX_classes.mk"

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simX/obj_dir/Vcache_simX_classes.mk
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# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See Vcache_simX.mk for the caller.
### Switches...
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Threaded output mode? 0/1/N threads (from --threads)
VM_THREADS = 0
# Tracing output mode? 0/1 (from --trace)
VM_TRACE = 1
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
Vcache_simX \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 \
Vcache_simX_VX_dcache_request_inter \
Vcache_simX_VX_Cache_Bank__pi9 \
Vcache_simX_VX_Cache_Bank__pi8 \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
Vcache_simX__Trace \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
Vcache_simX__Syms \
Vcache_simX__Trace__Slow \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
verilated_vcd_c \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

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simX/obj_dir/args.d
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args.o: ../args.cpp ../include/args.h

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simX/obj_dir/core.d
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core.o: ../core.cpp ../include/types.h ../include/util.h \
../include/types.h ../include/archdef.h ../include/mem.h \
../include/enc.h ../include/instruction.h ../include/trace.h \
../include/obj.h ../include/archdef.h ../include/enc.h \
../include/asm-tokens.h ../include/core.h ../include/mem.h \
../include/debug.h Vcache_simX.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated_vcd_c.h \
/usr/share/verilator/include/verilated.h ../include/debug.h

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simX/obj_dir/enc.d
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enc.o: ../enc.cpp ../include/debug.h ../include/types.h ../include/util.h \
../include/types.h ../include/enc.h ../include/instruction.h \
../include/trace.h ../include/obj.h ../include/archdef.h \
../include/enc.h ../include/asm-tokens.h ../include/archdef.h \
../include/instruction.h

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simX/obj_dir/instruction.d
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instruction.o: ../instruction.cpp ../include/instruction.h \
../include/types.h ../include/trace.h ../include/obj.h \
../include/archdef.h ../include/instruction.h ../include/enc.h \
../include/obj.h ../include/asm-tokens.h ../include/core.h \
../include/mem.h ../include/debug.h Vcache_simX.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated_vcd_c.h \
/usr/share/verilator/include/verilated.h ../include/harpfloat.h \
../include/debug.h

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simX/obj_dir/mem.d
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mem.o: ../mem.cpp ../include/debug.h ../include/types.h ../include/util.h \
../include/types.h ../include/mem.h ../include/core.h \
../include/archdef.h ../include/enc.h ../include/instruction.h \
../include/trace.h ../include/obj.h ../include/asm-tokens.h \
../include/mem.h ../include/debug.h Vcache_simX.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated_vcd_c.h \
/usr/share/verilator/include/verilated.h

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simX/obj_dir/simX.d
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simX.o: ../simX.cpp ../include/debug.h ../include/types.h \
../include/core.h ../include/types.h ../include/archdef.h \
../include/enc.h ../include/instruction.h ../include/trace.h \
../include/obj.h ../include/asm-tokens.h ../include/mem.h \
../include/debug.h Vcache_simX.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated_vcd_c.h \
/usr/share/verilator/include/verilated.h ../include/enc.h \
../include/instruction.h ../include/mem.h ../include/obj.h \
../include/archdef.h ../include/args.h ../include/help.h

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simX/obj_dir/util.d
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util.o: ../util.cpp ../include/types.h ../include/util.h \
../include/types.h

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simX/obj_dir/verilated.d
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verilated.o: /usr/share/verilator/include/verilated.cpp \
/usr/share/verilator/include/verilated_imp.h \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilated_heavy.h \
/usr/share/verilator/include/verilated_syms.h

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simX/obj_dir/verilated_vcd_c.d
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verilated_vcd_c.o: /usr/share/verilator/include/verilated_vcd_c.cpp \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilated_vcd_c.h

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simX/riscv_tests/rv32ui-p-add.dump
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rv32ui-p-add: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 80000f17 auipc t5,0x80000
80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054c63 bltz a0,800000cc <reset_vector+0x80>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 05d00893 li a7,93
800000c4: 00000513 li a0,0
800000c8: 00000073 ecall
800000cc: 80000297 auipc t0,0x80000
800000d0: f3428293 addi t0,t0,-204 # 0 <_start-0x80000000>
800000d4: 00028e63 beqz t0,800000f0 <reset_vector+0xa4>
800000d8: 10529073 csrw stvec,t0
800000dc: 0000b2b7 lui t0,0xb
800000e0: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000e4: 30229073 csrw medeleg,t0
800000e8: 30202373 csrr t1,medeleg
800000ec: f46298e3 bne t0,t1,8000003c <handle_exception>
800000f0: 30005073 csrwi mstatus,0
800000f4: 00000297 auipc t0,0x0
800000f8: 01428293 addi t0,t0,20 # 80000108 <test_2>
800000fc: 34129073 csrw mepc,t0
80000100: f1402573 csrr a0,mhartid
80000104: 30200073 mret
80000108 <test_2>:
80000108: 00000093 li ra,0
8000010c: 00000113 li sp,0
80000110: 00208733 add a4,ra,sp
80000114: 00000e93 li t4,0
80000118: 00200193 li gp,2
8000011c: 4dd71663 bne a4,t4,800005e8 <fail>
80000120 <test_3>:
80000120: 00100093 li ra,1
80000124: 00100113 li sp,1
80000128: 00208733 add a4,ra,sp
8000012c: 00200e93 li t4,2
80000130: 00300193 li gp,3
80000134: 4bd71a63 bne a4,t4,800005e8 <fail>
80000138 <test_4>:
80000138: 00300093 li ra,3
8000013c: 00700113 li sp,7
80000140: 00208733 add a4,ra,sp
80000144: 00a00e93 li t4,10
80000148: 00400193 li gp,4
8000014c: 49d71e63 bne a4,t4,800005e8 <fail>
80000150 <test_5>:
80000150: 00000093 li ra,0
80000154: ffff8137 lui sp,0xffff8
80000158: 00208733 add a4,ra,sp
8000015c: ffff8eb7 lui t4,0xffff8
80000160: 00500193 li gp,5
80000164: 49d71263 bne a4,t4,800005e8 <fail>
80000168 <test_6>:
80000168: 800000b7 lui ra,0x80000
8000016c: 00000113 li sp,0
80000170: 00208733 add a4,ra,sp
80000174: 80000eb7 lui t4,0x80000
80000178: 00600193 li gp,6
8000017c: 47d71663 bne a4,t4,800005e8 <fail>
80000180 <test_7>:
80000180: 800000b7 lui ra,0x80000
80000184: ffff8137 lui sp,0xffff8
80000188: 00208733 add a4,ra,sp
8000018c: 7fff8eb7 lui t4,0x7fff8
80000190: 00700193 li gp,7
80000194: 45d71a63 bne a4,t4,800005e8 <fail>
80000198 <test_8>:
80000198: 00000093 li ra,0
8000019c: 00008137 lui sp,0x8
800001a0: fff10113 addi sp,sp,-1 # 7fff <_start-0x7fff8001>
800001a4: 00208733 add a4,ra,sp
800001a8: 00008eb7 lui t4,0x8
800001ac: fffe8e93 addi t4,t4,-1 # 7fff <_start-0x7fff8001>
800001b0: 00800193 li gp,8
800001b4: 43d71a63 bne a4,t4,800005e8 <fail>
800001b8 <test_9>:
800001b8: 800000b7 lui ra,0x80000
800001bc: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff>
800001c0: 00000113 li sp,0
800001c4: 00208733 add a4,ra,sp
800001c8: 80000eb7 lui t4,0x80000
800001cc: fffe8e93 addi t4,t4,-1 # 7fffffff <_end+0xffffdfff>
800001d0: 00900193 li gp,9
800001d4: 41d71a63 bne a4,t4,800005e8 <fail>
800001d8 <test_10>:
800001d8: 800000b7 lui ra,0x80000
800001dc: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff>
800001e0: 00008137 lui sp,0x8
800001e4: fff10113 addi sp,sp,-1 # 7fff <_start-0x7fff8001>
800001e8: 00208733 add a4,ra,sp
800001ec: 80008eb7 lui t4,0x80008
800001f0: ffee8e93 addi t4,t4,-2 # 80007ffe <_end+0x5ffe>
800001f4: 00a00193 li gp,10
800001f8: 3fd71863 bne a4,t4,800005e8 <fail>
800001fc <test_11>:
800001fc: 800000b7 lui ra,0x80000
80000200: 00008137 lui sp,0x8
80000204: fff10113 addi sp,sp,-1 # 7fff <_start-0x7fff8001>
80000208: 00208733 add a4,ra,sp
8000020c: 80008eb7 lui t4,0x80008
80000210: fffe8e93 addi t4,t4,-1 # 80007fff <_end+0x5fff>
80000214: 00b00193 li gp,11
80000218: 3dd71863 bne a4,t4,800005e8 <fail>
8000021c <test_12>:
8000021c: 800000b7 lui ra,0x80000
80000220: fff08093 addi ra,ra,-1 # 7fffffff <_end+0xffffdfff>
80000224: ffff8137 lui sp,0xffff8
80000228: 00208733 add a4,ra,sp
8000022c: 7fff8eb7 lui t4,0x7fff8
80000230: fffe8e93 addi t4,t4,-1 # 7fff7fff <_start-0x8001>
80000234: 00c00193 li gp,12
80000238: 3bd71863 bne a4,t4,800005e8 <fail>
8000023c <test_13>:
8000023c: 00000093 li ra,0
80000240: fff00113 li sp,-1
80000244: 00208733 add a4,ra,sp
80000248: fff00e93 li t4,-1
8000024c: 00d00193 li gp,13
80000250: 39d71c63 bne a4,t4,800005e8 <fail>
80000254 <test_14>:
80000254: fff00093 li ra,-1
80000258: 00100113 li sp,1
8000025c: 00208733 add a4,ra,sp
80000260: 00000e93 li t4,0
80000264: 00e00193 li gp,14
80000268: 39d71063 bne a4,t4,800005e8 <fail>
8000026c <test_15>:
8000026c: fff00093 li ra,-1
80000270: fff00113 li sp,-1
80000274: 00208733 add a4,ra,sp
80000278: ffe00e93 li t4,-2
8000027c: 00f00193 li gp,15
80000280: 37d71463 bne a4,t4,800005e8 <fail>
80000284 <test_16>:
80000284: 00100093 li ra,1
80000288: 80000137 lui sp,0x80000
8000028c: fff10113 addi sp,sp,-1 # 7fffffff <_end+0xffffdfff>
80000290: 00208733 add a4,ra,sp
80000294: 80000eb7 lui t4,0x80000
80000298: 01000193 li gp,16
8000029c: 35d71663 bne a4,t4,800005e8 <fail>
800002a0 <test_17>:
800002a0: 00d00093 li ra,13
800002a4: 00b00113 li sp,11
800002a8: 002080b3 add ra,ra,sp
800002ac: 01800e93 li t4,24
800002b0: 01100193 li gp,17
800002b4: 33d09a63 bne ra,t4,800005e8 <fail>
800002b8 <test_18>:
800002b8: 00e00093 li ra,14
800002bc: 00b00113 li sp,11
800002c0: 00208133 add sp,ra,sp
800002c4: 01900e93 li t4,25
800002c8: 01200193 li gp,18
800002cc: 31d11e63 bne sp,t4,800005e8 <fail>
800002d0 <test_19>:
800002d0: 00d00093 li ra,13
800002d4: 001080b3 add ra,ra,ra
800002d8: 01a00e93 li t4,26
800002dc: 01300193 li gp,19
800002e0: 31d09463 bne ra,t4,800005e8 <fail>
800002e4 <test_20>:
800002e4: 00000213 li tp,0
800002e8: 00d00093 li ra,13
800002ec: 00b00113 li sp,11
800002f0: 00208733 add a4,ra,sp
800002f4: 00070313 mv t1,a4
800002f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
800002fc: 00200293 li t0,2
80000300: fe5214e3 bne tp,t0,800002e8 <test_20+0x4>
80000304: 01800e93 li t4,24
80000308: 01400193 li gp,20
8000030c: 2dd31e63 bne t1,t4,800005e8 <fail>
80000310 <test_21>:
80000310: 00000213 li tp,0
80000314: 00e00093 li ra,14
80000318: 00b00113 li sp,11
8000031c: 00208733 add a4,ra,sp
80000320: 00000013 nop
80000324: 00070313 mv t1,a4
80000328: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
8000032c: 00200293 li t0,2
80000330: fe5212e3 bne tp,t0,80000314 <test_21+0x4>
80000334: 01900e93 li t4,25
80000338: 01500193 li gp,21
8000033c: 2bd31663 bne t1,t4,800005e8 <fail>
80000340 <test_22>:
80000340: 00000213 li tp,0
80000344: 00f00093 li ra,15
80000348: 00b00113 li sp,11
8000034c: 00208733 add a4,ra,sp
80000350: 00000013 nop
80000354: 00000013 nop
80000358: 00070313 mv t1,a4
8000035c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
80000360: 00200293 li t0,2
80000364: fe5210e3 bne tp,t0,80000344 <test_22+0x4>
80000368: 01a00e93 li t4,26
8000036c: 01600193 li gp,22
80000370: 27d31c63 bne t1,t4,800005e8 <fail>
80000374 <test_23>:
80000374: 00000213 li tp,0
80000378: 00d00093 li ra,13
8000037c: 00b00113 li sp,11
80000380: 00208733 add a4,ra,sp
80000384: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
80000388: 00200293 li t0,2
8000038c: fe5216e3 bne tp,t0,80000378 <test_23+0x4>
80000390: 01800e93 li t4,24
80000394: 01700193 li gp,23
80000398: 25d71863 bne a4,t4,800005e8 <fail>
8000039c <test_24>:
8000039c: 00000213 li tp,0
800003a0: 00e00093 li ra,14
800003a4: 00b00113 li sp,11
800003a8: 00000013 nop
800003ac: 00208733 add a4,ra,sp
800003b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
800003b4: 00200293 li t0,2
800003b8: fe5214e3 bne tp,t0,800003a0 <test_24+0x4>
800003bc: 01900e93 li t4,25
800003c0: 01800193 li gp,24
800003c4: 23d71263 bne a4,t4,800005e8 <fail>
800003c8 <test_25>:
800003c8: 00000213 li tp,0
800003cc: 00f00093 li ra,15
800003d0: 00b00113 li sp,11
800003d4: 00000013 nop
800003d8: 00000013 nop
800003dc: 00208733 add a4,ra,sp
800003e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
800003e4: 00200293 li t0,2
800003e8: fe5212e3 bne tp,t0,800003cc <test_25+0x4>
800003ec: 01a00e93 li t4,26
800003f0: 01900193 li gp,25
800003f4: 1fd71a63 bne a4,t4,800005e8 <fail>
800003f8 <test_26>:
800003f8: 00000213 li tp,0
800003fc: 00d00093 li ra,13
80000400: 00000013 nop
80000404: 00b00113 li sp,11
80000408: 00208733 add a4,ra,sp
8000040c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
80000410: 00200293 li t0,2
80000414: fe5214e3 bne tp,t0,800003fc <test_26+0x4>
80000418: 01800e93 li t4,24
8000041c: 01a00193 li gp,26
80000420: 1dd71463 bne a4,t4,800005e8 <fail>
80000424 <test_27>:
80000424: 00000213 li tp,0
80000428: 00e00093 li ra,14
8000042c: 00000013 nop
80000430: 00b00113 li sp,11
80000434: 00000013 nop
80000438: 00208733 add a4,ra,sp
8000043c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
80000440: 00200293 li t0,2
80000444: fe5212e3 bne tp,t0,80000428 <test_27+0x4>
80000448: 01900e93 li t4,25
8000044c: 01b00193 li gp,27
80000450: 19d71c63 bne a4,t4,800005e8 <fail>
80000454 <test_28>:
80000454: 00000213 li tp,0
80000458: 00f00093 li ra,15
8000045c: 00000013 nop
80000460: 00000013 nop
80000464: 00b00113 li sp,11
80000468: 00208733 add a4,ra,sp
8000046c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
80000470: 00200293 li t0,2
80000474: fe5212e3 bne tp,t0,80000458 <test_28+0x4>
80000478: 01a00e93 li t4,26
8000047c: 01c00193 li gp,28
80000480: 17d71463 bne a4,t4,800005e8 <fail>
80000484 <test_29>:
80000484: 00000213 li tp,0
80000488: 00b00113 li sp,11
8000048c: 00d00093 li ra,13
80000490: 00208733 add a4,ra,sp
80000494: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
80000498: 00200293 li t0,2
8000049c: fe5216e3 bne tp,t0,80000488 <test_29+0x4>
800004a0: 01800e93 li t4,24
800004a4: 01d00193 li gp,29
800004a8: 15d71063 bne a4,t4,800005e8 <fail>
800004ac <test_30>:
800004ac: 00000213 li tp,0
800004b0: 00b00113 li sp,11
800004b4: 00e00093 li ra,14
800004b8: 00000013 nop
800004bc: 00208733 add a4,ra,sp
800004c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
800004c4: 00200293 li t0,2
800004c8: fe5214e3 bne tp,t0,800004b0 <test_30+0x4>
800004cc: 01900e93 li t4,25
800004d0: 01e00193 li gp,30
800004d4: 11d71a63 bne a4,t4,800005e8 <fail>
800004d8 <test_31>:
800004d8: 00000213 li tp,0
800004dc: 00b00113 li sp,11
800004e0: 00f00093 li ra,15
800004e4: 00000013 nop
800004e8: 00000013 nop
800004ec: 00208733 add a4,ra,sp
800004f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
800004f4: 00200293 li t0,2
800004f8: fe5212e3 bne tp,t0,800004dc <test_31+0x4>
800004fc: 01a00e93 li t4,26
80000500: 01f00193 li gp,31
80000504: 0fd71263 bne a4,t4,800005e8 <fail>
80000508 <test_32>:
80000508: 00000213 li tp,0
8000050c: 00b00113 li sp,11
80000510: 00000013 nop
80000514: 00d00093 li ra,13
80000518: 00208733 add a4,ra,sp
8000051c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
80000520: 00200293 li t0,2
80000524: fe5214e3 bne tp,t0,8000050c <test_32+0x4>
80000528: 01800e93 li t4,24
8000052c: 02000193 li gp,32
80000530: 0bd71c63 bne a4,t4,800005e8 <fail>
80000534 <test_33>:
80000534: 00000213 li tp,0
80000538: 00b00113 li sp,11
8000053c: 00000013 nop
80000540: 00e00093 li ra,14
80000544: 00000013 nop
80000548: 00208733 add a4,ra,sp
8000054c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
80000550: 00200293 li t0,2
80000554: fe5212e3 bne tp,t0,80000538 <test_33+0x4>
80000558: 01900e93 li t4,25
8000055c: 02100193 li gp,33
80000560: 09d71463 bne a4,t4,800005e8 <fail>
80000564 <test_34>:
80000564: 00000213 li tp,0
80000568: 00b00113 li sp,11
8000056c: 00000013 nop
80000570: 00000013 nop
80000574: 00f00093 li ra,15
80000578: 00208733 add a4,ra,sp
8000057c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff>
80000580: 00200293 li t0,2
80000584: fe5212e3 bne tp,t0,80000568 <test_34+0x4>
80000588: 01a00e93 li t4,26
8000058c: 02200193 li gp,34
80000590: 05d71c63 bne a4,t4,800005e8 <fail>
80000594 <test_35>:
80000594: 00f00093 li ra,15
80000598: 00100133 add sp,zero,ra
8000059c: 00f00e93 li t4,15
800005a0: 02300193 li gp,35
800005a4: 05d11263 bne sp,t4,800005e8 <fail>
800005a8 <test_36>:
800005a8: 02000093 li ra,32
800005ac: 00008133 add sp,ra,zero
800005b0: 02000e93 li t4,32
800005b4: 02400193 li gp,36
800005b8: 03d11863 bne sp,t4,800005e8 <fail>
800005bc <test_37>:
800005bc: 000000b3 add ra,zero,zero
800005c0: 00000e93 li t4,0
800005c4: 02500193 li gp,37
800005c8: 03d09063 bne ra,t4,800005e8 <fail>
800005cc <test_38>:
800005cc: 01000093 li ra,16
800005d0: 01e00113 li sp,30
800005d4: 00208033 add zero,ra,sp
800005d8: 00000e93 li t4,0
800005dc: 02600193 li gp,38
800005e0: 01d01463 bne zero,t4,800005e8 <fail>
800005e4: 02301063 bne zero,gp,80000604 <pass>
800005e8 <fail>:
800005e8: 0ff0000f fence
800005ec: 00018063 beqz gp,800005ec <fail+0x4>
800005f0: 00119193 slli gp,gp,0x1
800005f4: 0011e193 ori gp,gp,1
800005f8: 05d00893 li a7,93
800005fc: 00018513 mv a0,gp
80000600: 00000073 ecall
80000604 <pass>:
80000604: 0ff0000f fence
80000608: 00100193 li gp,1
8000060c: 05d00893 li a7,93
80000610: 00000513 li a0,0
80000614: 00000073 ecall
80000618: c0001073 unimp
8000061c: 0000 unimp
8000061e: 0000 unimp
80000620: 0000 unimp
80000622: 0000 unimp
80000624: 0000 unimp
80000626: 0000 unimp
80000628: 0000 unimp
8000062a: 0000 unimp
8000062c: 0000 unimp
8000062e: 0000 unimp
80000630: 0000 unimp
80000632: 0000 unimp
80000634: 0000 unimp
80000636: 0000 unimp
80000638: 0000 unimp
8000063a: 0000 unimp
8000063c: 0000 unimp
8000063e: 0000 unimp
80000640: 0000 unimp
80000642: 0000 unimp

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