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minor update

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tinebp 2024-11-22 11:12:17 -08:00
parent 7c4ce74801
commit 3e4bbfc9f0
1 changed files with 5 additions and 2 deletions
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7
hw/rtl/libs/VX_fifo_queue.sv
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@ -110,9 +110,12 @@ module VX_fifo_queue #(
if (OUT_REG != 0) begin : g_out_reg
reg [DATAW-1:0] data_out_r;
wire going_empty = (ALM_EMPTY == 1) ? alm_empty : (size[ADDRW-1:0] == ADDRW'(1));
wire bypass = push && (empty || (going_empty && pop));
always @(posedge clk) begin
if (pop || (push && empty)) begin
data_out_r <= (empty || going_empty) ? data_in : data_out_w;
if (bypass) begin
data_out_r <= data_in;
end else if (pop) begin
data_out_r <= data_out_w;
end
end
assign data_out = data_out_r;