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Merge branch 'graphics' of https://github.com/vortexgpgpu/vortex-dev into graphics

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This commit is contained in:
Blaise Tine 2022-09-01 19:39:03 -04:00
commit a5079c16d9
34 changed files with 862 additions and 2581 deletions
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24
hw/afu/opae/vortex_afu.sv
View file

@ -122,7 +122,7 @@ wire [`VX_MEM_DATA_WIDTH-1:0] vx_mem_rsp_data;
wire [`VX_MEM_TAG_WIDTH-1:0] vx_mem_rsp_tag;
wire vx_mem_rsp_ready;
reg vx_start;
reg vx_reset;
wire vx_busy;
// CMD variables //////////////////////////////////////////////////////////////
@ -299,7 +299,7 @@ end
wire cmd_mem_rd_done;
reg cmd_mem_wr_done;
wire cmd_run_done;
reg vx_started;
reg vx_running;
reg [$clog2(`RESET_DELAY+1)-1:0] vx_reset_ctr;
always @(posedge clk) begin
@ -316,8 +316,8 @@ wire [CMD_TYPE_WIDTH-1:0] cmd_type = is_mmio_wr_cmd ? CMD_TYPE_WIDTH'(cp2af_sRxP
always @(posedge clk) begin
if (reset) begin
state <= STATE_IDLE;
vx_started <= 0;
vx_start <= 0;
vx_running <= 0;
vx_reset <= 0;
end else begin
case (state)
STATE_IDLE: begin
@ -344,7 +344,7 @@ always @(posedge clk) begin
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: STATE RUN\n", $time));
`endif
vx_start <= 1;
vx_reset <= 1;
state <= STATE_RUN;
end
default: begin
@ -380,9 +380,9 @@ always @(posedge clk) begin
STATE_RUN: begin
// vortex reset cycles
if (vx_started) begin
if (vx_running) begin
if (cmd_run_done) begin
vx_started <= 0;
vx_running <= 0;
state <= STATE_IDLE;
`ifdef DBG_TRACE_AFU
`TRACE(2, ("%d: STATE IDLE\n", $time));
@ -390,8 +390,8 @@ always @(posedge clk) begin
end
end else begin
if (vx_reset_ctr == (`RESET_DELAY-1)) begin
vx_started <= 1;
vx_start <= 0;
vx_running <= 1;
vx_reset <= 0;
end
end
end
@ -479,7 +479,7 @@ wire vx_mem_is_cout;
wire vx_mem_req_valid_qual;
wire vx_mem_req_ready_qual;
assign vx_mem_req_valid_qual = vx_mem_req_valid && ~vx_mem_is_cout && vx_started;
assign vx_mem_req_valid_qual = vx_mem_req_valid && ~vx_mem_is_cout && vx_running;
VX_mem_adapter #(
.SRC_DATA_WIDTH (`VX_MEM_DATA_WIDTH),
@ -885,7 +885,7 @@ Vortex vortex (
`SCOPE_BIND_afu_vortex
.clk (clk),
.reset (reset || vx_start),
.reset (reset || vx_reset),
// Memory request
.mem_req_valid (vx_mem_req_valid),
@ -932,7 +932,7 @@ assign vx_mem_req_ready = vx_mem_is_cout ? ~cout_q_full : vx_mem_req_ready_qual;
wire [`VX_MEM_BYTEEN_WIDTH-1:0][7:0] vx_mem_req_data_m = vx_mem_req_data;
wire [7:0] cout_char = vx_mem_req_data_m[cout_tid];
wire cout_q_push = vx_mem_req_valid && vx_mem_is_cout && vx_started && ~cout_q_full;
wire cout_q_push = vx_mem_req_valid && vx_mem_is_cout && vx_running && ~cout_q_full;
wire cout_q_pop = cp2af_sRxPort.c0.mmioRdValid
&& (mmio_hdr.address == MMIO_STATUS)

381
hw/afu/xrt/VX_afu_control.sv Normal file
View file

@ -0,0 +1,381 @@
`include "VX_define.vh"
module VX_afu_control #(
parameter AXI_ADDR_WIDTH = 6,
parameter AXI_DATA_WIDTH = 32
) (
// axi4 lite slave signals
input wire clk,
input wire reset,
input wire clk_en,
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire s_axi_awvalid,
output wire s_axi_awready,
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wvalid,
output wire s_axi_wready,
output wire [1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire s_axi_arvalid,
output wire s_axi_arready,
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [1:0] s_axi_rresp,
output wire s_axi_rvalid,
input wire s_axi_rready,
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle,
output wire interrupt,
output wire dcr_wr_valid,
output wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr,
output wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data
);
// Address Info
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : Low 32-bit Data signal of mem_addr
// 0x14 : High 32-bit Data signal of mem_addr
// 0x18 : Control signal of mem_addr
// 0x1C : Low 32-bit Data signal of dcr
// 0x20 : High 32-bit Data signal of dcr
// 0x24 : Control signal of dcr
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
// Parameter
localparam ADDR_BITS = 6;
localparam
ADDR_AP_CTRL = 6'h00,
ADDR_GIE = 6'h04,
ADDR_IER = 6'h08,
ADDR_ISR = 6'h0c,
ADDR_MEM_0 = 6'h10,
ADDR_MEM_1 = 6'h14,
ADDR_MEM_CTRL = 6'h18
ADDR_DCR_0 = 6'h1C,
ADDR_DCR_1 = 6'h20,
ADDR_DCR_CTRL = 6'h24;
localparam
WSTATE_IDLE = 2'd0,
WSTATE_DATA = 2'd1,
WSTATE_RESP = 2'd2;
localparam
RSTATE_IDLE = 2'd0,
RSTATE_DATA = 2'd1;
// Local signal
reg [1:0] wstate = WSTATE_IDLE;
reg [1:0] wstate_n;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs; // write address handshake
wire wd_hs; // write data handshake
reg [1:0] rstate = RSTATE_IDLE;
reg [1:0] rstate_n;
reg [31:0] rdata;
wire ar_hs; // read address handshake
wire [ADDR_BITS-1:0] raddr;
// internal registers
wire int_ap_idle;
wire int_ap_ready;
reg int_ap_done = 1'b0;
reg int_ap_start = 1'b0;
reg int_auto_restart = 1'b0;
reg int_gie = 2'b0;
reg [1:0] int_ier = 2'b0;
reg [1:0] int_isr = 2'b0;
reg [63:0] int_mem = 64'b0;
reg [31:0] int_dcra = 32'b0;
reg [31:0] int_dcrv = 32'b0;
// AXI Write FSM
assign s_axi_awready = (wstate == WSTATE_IDLE);
assign s_axi_wready = (wstate == WSTATE_DATA);
assign s_axi_bresp = 2'b00; // OKAY
assign s_axi_bvalid = (wstate == WSTATE_RESP);
assign wmask = {{8{s_axi_wstrb[3]}}, {8{s_axi_wstrb[2]}}, {8{s_axi_wstrb[1]}}, {8{s_axi_wstrb[0]}}};
assign aw_hs = s_axi_awvalid && s_axi_awready;
assign wd_hs = s_axi_wvalid && s_axi_wready;
// wstate
always @(posedge clk) begin
if (reset)
wstate <= WSTATE_IDLE;
else if (clk_en)
wstate <= wstate_n;
end
// wstate_n
always @(*) begin
case (wstate)
WSTATE_IDLE:
if (s_axi_awvalid)
wstate_n = WSTATE_DATA;
else
wstate_n = WSTATE_IDLE;
WSTATE_DATA:
if (s_axi_wvalid)
wstate_n = WSTATE_RESP;
else
wstate_n = WSTATE_DATA;
WSTATE_RESP:
if (s_axi_bready)
wstate_n = WSTATE_IDLE;
else
wstate_n = WSTATE_RESP;
default:
wstate_n = WSTATE_IDLE;
endcase
end
// waddr
always @(posedge clk) begin
if (clk_en) begin
if (aw_hs)
waddr <= s_axi_awaddr[ADDR_BITS-1:0];
end
end
// AXI Read FSM
assign s_axi_arready = (rstate == RSTATE_IDLE);
assign s_axi_rdata = rdata;
assign s_axi_rresp = 2'b00; // OKAY
assign s_axi_rvalid = (rstate == RSTATE_DATA);
assign ar_hs = s_axi_arvalid && s_axi_arready;
assign raddr = s_axi_araddr[ADDR_BITS-1:0];
// rstate
always @(posedge clk) begin
if (reset)
rstate <= RSTATE_IDLE;
else if (clk_en)
rstate <= rstate_n;
end
// rstate_n
always @(*) begin
case (rstate)
RSTATE_IDLE:
if (s_axi_arvalid)
rstate_n = RSTATE_DATA;
else
rstate_n = RSTATE_IDLE;
RSTATE_DATA:
if (s_axi_rready & s_axi_rvalid)
rstate_n = RSTATE_IDLE;
else
rstate_n = RSTATE_DATA;
default:
rstate_n = RSTATE_IDLE;
endcase
end
// rdata
always @(posedge clk) begin
if (clk_en) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
ADDR_DCR_0: begin
rdata <= int_dcra;
end
ADDR_DCR_1: begin
rdata <= int_dcrv;
end
endcase
end
end
end
// Register logic
assign interrupt = int_gie & (| int_isr);
assign ap_start = int_ap_start;
assign int_ap_idle = ap_idle;
assign int_ap_ready = ap_ready;
// int_ap_start
always @(posedge clk) begin
if (reset)
int_ap_start <= 1'b0;
else if (clk_en) begin
if (wd_hs && waddr == ADDR_AP_CTRL && s_axi_wstrb[0] && s_axi_wdata[0])
int_ap_start <= 1'b1;
else if (int_ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
end
// int_ap_done
always @(posedge clk) begin
if (reset)
int_ap_done <= 1'b0;
else if (clk_en) begin
if (ap_done)
int_ap_done <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
int_ap_done <= 1'b0; // clear on read
end
end
// int_auto_restart
always @(posedge clk) begin
if (reset)
int_auto_restart <= 1'b0;
else if (clk_en) begin
if (wd_hs && waddr == ADDR_AP_CTRL && s_axi_wstrb[0])
int_auto_restart <= s_axi_wdata[7];
end
end
// int_gie
always @(posedge clk) begin
if (reset)
int_gie <= 1'b0;
else if (clk_en) begin
if (wd_hs && waddr == ADDR_GIE && s_axi_wstrb[0])
int_gie <= s_axi_wdata[0];
end
end
// int_ier
always @(posedge clk) begin
if (reset)
int_ier <= 1'b0;
else if (clk_en) begin
if (wd_hs && waddr == ADDR_IER && s_axi_wstrb[0])
int_ier <= s_axi_wdata[1:0];
end
end
// int_isr[0]
always @(posedge clk) begin
if (reset)
int_isr[0] <= 1'b0;
else if (clk_en) begin
if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (wd_hs && waddr == ADDR_ISR && s_axi_wstrb[0])
int_isr[0] <= int_isr[0] ^ s_axi_wdata[0]; // toggle on write
end
end
// int_isr[1]
always @(posedge clk) begin
if (reset)
int_isr[1] <= 1'b0;
else if (clk_en) begin
if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (wd_hs && waddr == ADDR_ISR && s_axi_wstrb[0])
int_isr[1] <= int_isr[1] ^ s_axi_wdata[1]; // toggle on write
end
end
// int_mem[31:0]
always @(posedge clk) begin
if (reset)
int_mem[31:0] <= 0;
else if (clk_en) begin
if (wd_hs && waddr == ADDR_MEM_0)
int_mem[31:0] <= (s_axi_wdata & wmask) | (int_mem[31:0] & ~wmask);
end
end
// int_mem[63:32]
always @(posedge clk) begin
if (reset)
int_mem[63:32] <= 0;
else if (clk_en) begin
if (wd_hs && waddr == ADDR_MEM_1)
int_mem[63:32] <= (s_axi_wdata & wmask) | (int_mem[63:32] & ~wmask);
end
end
// int_dcra
always @(posedge clk) begin
if (reset)
int_dcra <= 0;
else if (clk_en) begin
if (wd_hs && waddr == ADDR_DCR_0)
int_dcra <= (s_axi_wdata & wmask) | (int_dcra & ~wmask);
end
end
// int_dcrv
always @(posedge clk) begin
if (reset)
int_dcrv <= 0;
else if (clk_en) begin
if (wd_hs && waddr == ADDR_DCR_1)
int_dcrv <= (s_axi_wdata & wmask) | (int_dcrv & ~wmask);
end
end
reg [31:0] dcrv_wmask;
wire [31:0] dcrv_wmask_n = dcrv_wmask | wmask;
wire dcrv_wmask_full = (dcrv_wmask_n == {32{1'b1}});
reg dcr_wr_valid_r;
always @(posedge clk) begin
if (reset) begin
dcr_wr_valid_r <= 0;
dcrv_wmask <= 0;
end else begin
if (wd_hs && waddr == ADDR_DCR_1) begin
if (dcrv_wmask_full)
dcrv_wmask <= 0;
else
dcrv_wmask <= dcrv_wmask_n;
end
dcr_wr_valid_r <= dcrv_wmask_full;
end
end
assign dcr_wr_valid = dcr_wr_valid_r;
assign dcr_wr_addr = int_dcra;
assign dcr_wr_data = int_dcrv;
endmodule

274
hw/afu/xrt/krnl_axi_read_master.sv
View file

@ -1,274 +0,0 @@
/**
* Copyright (C) 2019-2021 Xilinx, Inc
*
* Licensed under the Apache License, Version 2.0 (the "License"). You may
* not use this file except in compliance with the License. A copy of the
* License is located at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*/
///////////////////////////////////////////////////////////////////////////////
// Description: This is a multi-threaded AXI4 read master. Each channel will
// issue commands on a different IDs. As a result data may arrive out of
// order. The amount of data requested is equal to the ctrl_length variable.
// Prog full is set and sampled such that the FIFO will never overflow. Thus
// rready can be always asserted for better timing.
///////////////////////////////////////////////////////////////////////////////
`default_nettype none
module krnl_axi_read_master #(
parameter integer C_ID_WIDTH = 1, // Must be >= $clog2(C_NUM_CHANNELS)
parameter integer C_ADDR_WIDTH = 64,
parameter integer C_DATA_WIDTH = 32,
parameter integer C_NUM_CHANNELS = 2, // Only 2 tested.
parameter integer C_LENGTH_WIDTH = 32,
parameter integer C_BURST_LEN = 256, // Max AXI burst length for read commands
parameter integer C_LOG_BURST_LEN = 8,
parameter integer C_MAX_OUTSTANDING = 3
)
(
// System signals
input wire aclk,
input wire areset,
// Control signals
input wire ctrl_start,
output wire ctrl_done,
input wire [C_NUM_CHANNELS-1:0][C_ADDR_WIDTH-1:0] ctrl_offset,
input wire [C_LENGTH_WIDTH-1:0] ctrl_length,
input wire [C_NUM_CHANNELS-1:0] ctrl_prog_full,
// AXI4 master interface
output wire arvalid,
input wire arready,
output wire [C_ADDR_WIDTH-1:0] araddr,
output wire [C_ID_WIDTH-1:0] arid,
output wire [7:0] arlen,
output wire [2:0] arsize,
input wire rvalid,
output wire rready,
input wire [C_DATA_WIDTH - 1:0] rdata,
input wire rlast,
input wire [C_ID_WIDTH - 1:0] rid,
input wire [1:0] rresp,
// AXI4-Stream master interface, 1 interface per channel.
output wire [C_NUM_CHANNELS-1:0] m_tvalid,
input wire [C_NUM_CHANNELS-1:0] m_tready,
output wire [C_NUM_CHANNELS-1:0][C_DATA_WIDTH-1:0] m_tdata
);
timeunit 1ps;
timeprecision 1ps;
///////////////////////////////////////////////////////////////////////////////
// Local Parameters
///////////////////////////////////////////////////////////////////////////////
localparam integer LP_MAX_OUTSTANDING_CNTR_WIDTH = $clog2(C_MAX_OUTSTANDING+1);
localparam integer LP_TRANSACTION_CNTR_WIDTH = C_LENGTH_WIDTH-C_LOG_BURST_LEN;
///////////////////////////////////////////////////////////////////////////////
// Variables
///////////////////////////////////////////////////////////////////////////////
// Control logic
logic [C_NUM_CHANNELS-1:0] done = '0;
logic [LP_TRANSACTION_CNTR_WIDTH-1:0] num_full_bursts;
logic num_partial_bursts;
logic start = 1'b0;
logic [LP_TRANSACTION_CNTR_WIDTH-1:0] num_transactions;
logic has_partial_burst;
logic [C_LOG_BURST_LEN-1:0] final_burst_len;
logic single_transaction;
logic ar_idle = 1'b1;
logic ar_done;
// AXI Read Address Channel
logic fifo_stall;
logic arxfer;
logic arvalid_r = 1'b0;
logic [C_NUM_CHANNELS-1:0][C_ADDR_WIDTH-1:0] addr;
logic [C_ID_WIDTH-1:0] id = {C_ID_WIDTH{1'b1}};
logic [LP_TRANSACTION_CNTR_WIDTH-1:0] ar_transactions_to_go;
logic ar_final_transaction;
logic [C_NUM_CHANNELS-1:0] incr_ar_to_r_cnt;
logic [C_NUM_CHANNELS-1:0] decr_ar_to_r_cnt;
logic [C_NUM_CHANNELS-1:0] stall_ar;
logic [C_NUM_CHANNELS-1:0][LP_MAX_OUTSTANDING_CNTR_WIDTH-1:0] outstanding_vacancy_count;
// AXI Data Channel
logic [C_NUM_CHANNELS-1:0] tvalid;
logic [C_NUM_CHANNELS-1:0][C_DATA_WIDTH-1:0] tdata;
logic rxfer;
logic [C_NUM_CHANNELS-1:0] decr_r_transaction_cntr;
logic [C_NUM_CHANNELS-1:0][LP_TRANSACTION_CNTR_WIDTH-1:0] r_transactions_to_go;
logic [C_NUM_CHANNELS-1:0] r_final_transaction;
///////////////////////////////////////////////////////////////////////////////
// Control Logic
///////////////////////////////////////////////////////////////////////////////
always @(posedge aclk) begin
for (int i = 0; i < C_NUM_CHANNELS; i++) begin
done[i] <= rxfer & rlast & (rid == i) & r_final_transaction[i] ? 1'b1 :
ctrl_done ? 1'b0 : done[i];
end
end
assign ctrl_done = &done;
// Determine how many full burst to issue and if there are any partial bursts.
assign num_full_bursts = ctrl_length[C_LOG_BURST_LEN+:C_LENGTH_WIDTH-C_LOG_BURST_LEN];
assign num_partial_bursts = ctrl_length[0+:C_LOG_BURST_LEN] ? 1'b1 : 1'b0;
always @(posedge aclk) begin
start <= ctrl_start;
num_transactions <= (num_partial_bursts == 1'b0) ? num_full_bursts - 1'b1 : num_full_bursts;
has_partial_burst <= num_partial_bursts;
final_burst_len <= ctrl_length[0+:C_LOG_BURST_LEN] - 1'b1;
end
// Special case if there is only 1 AXI transaction.
assign single_transaction = (num_transactions == {LP_TRANSACTION_CNTR_WIDTH{1'b0}}) ? 1'b1 : 1'b0;
///////////////////////////////////////////////////////////////////////////////
// AXI Read Address Channel
///////////////////////////////////////////////////////////////////////////////
assign arvalid = arvalid_r;
assign araddr = addr[id];
assign arlen = ar_final_transaction || (start & single_transaction) ? final_burst_len : C_BURST_LEN - 1;
assign arsize = $clog2((C_DATA_WIDTH/8));
assign arid = id;
assign arxfer = arvalid & arready;
assign fifo_stall = ctrl_prog_full[id];
always @(posedge aclk) begin
if (areset) begin
arvalid_r <= 1'b0;
end
else begin
arvalid_r <= ~ar_idle & ~stall_ar[id] & ~arvalid_r & ~fifo_stall ? 1'b1 :
arready ? 1'b0 : arvalid_r;
end
end
// When ar_idle, there are no transactions to issue.
always @(posedge aclk) begin
if (areset) begin
ar_idle <= 1'b1;
end
else begin
ar_idle <= start ? 1'b0 :
ar_done ? 1'b1 :
ar_idle;
end
end
// each channel is assigned a different id. The transactions are interleaved.
always @(posedge aclk) begin
if (start) begin
id <= {C_ID_WIDTH{1'b1}};
end
else begin
id <= arxfer ? id - 1'b1 : id;
end
end
// Increment to next address after each transaction is issued.
always @(posedge aclk) begin
for (int i = 0; i < C_NUM_CHANNELS; i++) begin
addr[i] <= ctrl_start ? ctrl_offset[i] :
arxfer && (id == i) ? addr[i] + C_BURST_LEN*C_DATA_WIDTH/8 :
addr[i];
end
end
// Counts down the number of transactions to send.
krnl_counter #(
.C_WIDTH ( LP_TRANSACTION_CNTR_WIDTH ) ,
.C_INIT ( {LP_TRANSACTION_CNTR_WIDTH{1'b0}} )
)
inst_ar_transaction_cntr (
.clk ( aclk ) ,
.clken ( 1'b1 ) ,
.rst ( areset ) ,
.load ( start ) ,
.incr ( 1'b0 ) ,
.decr ( arxfer && id == '0 ) ,
.load_value ( num_transactions ) ,
.count ( ar_transactions_to_go ) ,
.is_zero ( ar_final_transaction )
);
assign ar_done = ar_final_transaction && arxfer && id == 1'b0;
always_comb begin
for (int i = 0; i < C_NUM_CHANNELS; i++) begin
incr_ar_to_r_cnt[i] = rxfer & rlast & (rid == i);
decr_ar_to_r_cnt[i] = arxfer & (arid == i);
end
end
// Keeps track of the number of outstanding transactions. Stalls
// when the value is reached so that the FIFO won't overflow.
krnl_counter #(
.C_WIDTH ( LP_MAX_OUTSTANDING_CNTR_WIDTH ) ,
.C_INIT ( C_MAX_OUTSTANDING[0+:LP_MAX_OUTSTANDING_CNTR_WIDTH] )
)
inst_ar_to_r_transaction_cntr[C_NUM_CHANNELS-1:0] (
.clk ( aclk ) ,
.clken ( 1'b1 ) ,
.rst ( areset ) ,
.load ( 1'b0 ) ,
.incr ( incr_ar_to_r_cnt ) ,
.decr ( decr_ar_to_r_cnt ) ,
.load_value ( {LP_MAX_OUTSTANDING_CNTR_WIDTH{1'b0}} ) ,
.count ( outstanding_vacancy_count ) ,
.is_zero ( stall_ar )
);
///////////////////////////////////////////////////////////////////////////////
// AXI Read Channel
///////////////////////////////////////////////////////////////////////////////
assign m_tvalid = tvalid;
assign m_tdata = tdata;
always_comb begin
for (int i = 0; i < C_NUM_CHANNELS; i++) begin
tvalid[i] = rvalid && (rid == i);
tdata[i] = rdata;
end
end
// rready can remain high for optimal timing because ar transactions are not issued
// unless there is enough space in the FIFO.
assign rready = 1'b1;
assign rxfer = rready & rvalid;
always_comb begin
for (int i = 0; i < C_NUM_CHANNELS; i++) begin
decr_r_transaction_cntr[i] = rxfer & rlast & (rid == i);
end
end
krnl_counter #(
.C_WIDTH ( LP_TRANSACTION_CNTR_WIDTH ) ,
.C_INIT ( {LP_TRANSACTION_CNTR_WIDTH{1'b0}} )
)
inst_r_transaction_cntr[C_NUM_CHANNELS-1:0] (
.clk ( aclk ) ,
.clken ( 1'b1 ) ,
.rst ( areset ) ,
.load ( start ) ,
.incr ( 1'b0 ) ,
.decr ( decr_r_transaction_cntr ) ,
.load_value ( num_transactions ) ,
.count ( r_transactions_to_go ) ,
.is_zero ( r_final_transaction )
);
endmodule : krnl_axi_read_master
`default_nettype wire

276
hw/afu/xrt/krnl_axi_write_master.sv
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@ -1,276 +0,0 @@
/**
* Copyright (C) 2019-2021 Xilinx, Inc
*
* Licensed under the Apache License, Version 2.0 (the "License"). You may
* not use this file except in compliance with the License. A copy of the
* License is located at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*/
////////////////////////////////////////////////////////////
// Description: AXI4 Write Master. Takes a stream of data in,
// appends address information and sends it out.
`default_nettype none
module krnl_axi_write_master #(
parameter integer C_ADDR_WIDTH = 64,
parameter integer C_DATA_WIDTH = 32,
parameter integer C_MAX_LENGTH_WIDTH = 32,
parameter integer C_BURST_LEN = 256,
parameter integer C_LOG_BURST_LEN = 8
)
(
// Control interface
input wire ctrl_start,
input wire [C_ADDR_WIDTH-1:0] ctrl_offset,
input wire [C_MAX_LENGTH_WIDTH-1:0] ctrl_length,
output wire ctrl_done,
// AXI4-Stream interface
input wire s_tvalid,
input wire [C_DATA_WIDTH-1:0] s_tdata,
output wire s_tready,
// AXI Interface
input wire aclk,
input wire areset,
output wire [C_ADDR_WIDTH-1:0] awaddr,
output wire [7:0] awlen,
output wire [2:0] awsize,
output wire awvalid,
input wire awready,
output wire [C_DATA_WIDTH-1:0] wdata,
output wire [C_DATA_WIDTH/8-1:0] wstrb,
output wire wlast,
output wire wvalid,
input wire wready,
input wire [1:0] bresp,
input wire bvalid,
output wire bready
);
timeunit 1ps;
timeprecision 1ps;
/////////////////////////////////////////////////////////////////////////////
// Local Parameters
/////////////////////////////////////////////////////////////////////////////
localparam integer LP_LOG_MAX_W_TO_AW = 8; // Allow up to 256 outstanding w to aw transactions
localparam integer LP_TRANSACTION_CNTR_WIDTH = C_MAX_LENGTH_WIDTH-C_LOG_BURST_LEN;
/////////////////////////////////////////////////////////////////////////////
// Variables
/////////////////////////////////////////////////////////////////////////////
logic [LP_TRANSACTION_CNTR_WIDTH-1:0] num_full_bursts;
logic num_partial_bursts;
logic start = 1'b0;
logic [LP_TRANSACTION_CNTR_WIDTH-1:0] num_transactions;
logic has_partial_burst;
logic [C_LOG_BURST_LEN-1:0] final_burst_len;
logic single_transaction;
logic wxfer; // Unregistered write data transfer
logic wfirst = 1'b1;
logic load_burst_cntr;
logic [C_LOG_BURST_LEN-1:0] wxfers_to_go; // Used for simulation debug
logic [LP_TRANSACTION_CNTR_WIDTH-1:0] w_transactions_to_go;
logic w_final_transaction;
logic w_almost_final_transaction = 1'b0;
logic awxfer;
logic awvalid_r = 1'b0;
logic [C_ADDR_WIDTH-1:0] addr;
logic wfirst_d1 = 1'b0;
logic wfirst_pulse = 1'b0;
logic [LP_LOG_MAX_W_TO_AW-1:0] dbg_w_to_aw_outstanding;
logic idle_aw;
logic [LP_TRANSACTION_CNTR_WIDTH-1:0] aw_transactions_to_go;
logic aw_final_transaction;
wire bxfer;
logic [LP_TRANSACTION_CNTR_WIDTH-1:0] b_transactions_to_go;
logic b_final_transaction;
/////////////////////////////////////////////////////////////////////////////
// Control logic
/////////////////////////////////////////////////////////////////////////////
// Count the number of transfers and assert done when the last bvalid is received.
assign num_full_bursts = ctrl_length[C_LOG_BURST_LEN+:C_MAX_LENGTH_WIDTH-C_LOG_BURST_LEN];
assign num_partial_bursts = ctrl_length[0+:C_LOG_BURST_LEN] ? 1'b1 : 1'b0;
always @(posedge aclk) begin
start <= ctrl_start;
num_transactions <= (num_partial_bursts == 1'b0) ? num_full_bursts - 1'b1 : num_full_bursts;
has_partial_burst <= num_partial_bursts;
final_burst_len <= ctrl_length[0+:C_LOG_BURST_LEN] - 1'b1;
end
assign ctrl_done = bxfer & b_final_transaction;
assign single_transaction = (num_transactions == {LP_TRANSACTION_CNTR_WIDTH{1'b0}}) ? 1'b1 : 1'b0;
/////////////////////////////////////////////////////////////////////////////
// AXI Write Data Channel
/////////////////////////////////////////////////////////////////////////////
assign wvalid = s_tvalid;
assign wdata = s_tdata;
assign wstrb = {(C_DATA_WIDTH/8){1'b1}};
assign s_tready = wready;
assign wxfer = wvalid & wready;
always @(posedge aclk) begin
if (areset) begin
wfirst <= 1'b1;
end
else begin
wfirst <= wxfer ? wlast : wfirst;
end
end
// Load burst counter with partial burst if on final transaction or if there is only 1 transaction
assign load_burst_cntr = (wxfer & wlast & w_almost_final_transaction) || (start & single_transaction);
krnl_counter #(
.C_WIDTH ( C_LOG_BURST_LEN ) ,
.C_INIT ( {C_LOG_BURST_LEN{1'b1}} )
)
inst_burst_cntr (
.clk ( aclk ) ,
.clken ( 1'b1 ) ,
.rst ( areset ) ,
.load ( load_burst_cntr ) ,
.incr ( 1'b0 ) ,
.decr ( wxfer ) ,
.load_value ( final_burst_len ) ,
.count ( wxfers_to_go ) ,
.is_zero ( wlast )
);
krnl_counter #(
.C_WIDTH ( LP_TRANSACTION_CNTR_WIDTH ) ,
.C_INIT ( {LP_TRANSACTION_CNTR_WIDTH{1'b0}} )
)
inst_w_transaction_cntr (
.clk ( aclk ) ,
.clken ( 1'b1 ) ,
.rst ( areset ) ,
.load ( start ) ,
.incr ( 1'b0 ) ,
.decr ( wxfer & wlast ) ,
.load_value ( num_transactions ) ,
.count ( w_transactions_to_go ) ,
.is_zero ( w_final_transaction )
);
always @(posedge aclk) begin
w_almost_final_transaction <= (w_transactions_to_go == 1) ? 1'b1 : 1'b0;
end
/////////////////////////////////////////////////////////////////////////////
// AXI Write Address Channel
/////////////////////////////////////////////////////////////////////////////
// The address channel samples the data channel and send out transactions when
// first beat of wdata is asserted. This ensures that address requests are not
// sent without data on the way.
assign awvalid = awvalid_r;
assign awxfer = awvalid & awready;
always @(posedge aclk) begin
if (areset) begin
awvalid_r <= 1'b0;
end
else begin
awvalid_r <= ~idle_aw & ~awvalid_r ? 1'b1 :
awready ? 1'b0 :
awvalid_r;
end
end
assign awaddr = addr;
always @(posedge aclk) begin
addr <= ctrl_start ? ctrl_offset :
awxfer ? addr + C_BURST_LEN*C_DATA_WIDTH/8 :
addr;
end
assign awlen = aw_final_transaction || (start & single_transaction) ? final_burst_len : C_BURST_LEN - 1;
assign awsize = $clog2((C_DATA_WIDTH/8));
krnl_counter #(
.C_WIDTH (LP_LOG_MAX_W_TO_AW),
.C_INIT ({LP_LOG_MAX_W_TO_AW{1'b0}})
)
inst_w_to_aw_cntr (
.clk ( aclk ) ,
.clken ( 1'b1 ) ,
.rst ( areset ) ,
.load ( 1'b0 ) ,
.incr ( wfirst_pulse ) ,
.decr ( awxfer ) ,
.load_value ( ) ,
.count ( dbg_w_to_aw_outstanding ) ,
.is_zero ( idle_aw )
);
always @(posedge aclk) begin
wfirst_d1 <= wvalid & wfirst;
end
always @(posedge aclk) begin
wfirst_pulse <= wvalid & wfirst & ~wfirst_d1;
end
krnl_counter #(
.C_WIDTH ( LP_TRANSACTION_CNTR_WIDTH ) ,
.C_INIT ( {LP_TRANSACTION_CNTR_WIDTH{1'b0}} )
)
inst_aw_transaction_cntr (
.clk ( aclk ) ,
.clken ( 1'b1 ) ,
.rst ( areset ) ,
.load ( start ) ,
.incr ( 1'b0 ) ,
.decr ( awxfer ) ,
.load_value ( num_transactions ) ,
.count ( aw_transactions_to_go ) ,
.is_zero ( aw_final_transaction )
);
/////////////////////////////////////////////////////////////////////////////
// AXI Write Response Channel
/////////////////////////////////////////////////////////////////////////////
assign bready = 1'b1;
assign bxfer = bready & bvalid;
krnl_counter #(
.C_WIDTH ( LP_TRANSACTION_CNTR_WIDTH ) ,
.C_INIT ( {LP_TRANSACTION_CNTR_WIDTH{1'b0}} )
)
inst_b_transaction_cntr (
.clk ( aclk ) ,
.clken ( 1'b1 ) ,
.rst ( areset ) ,
.load ( start ) ,
.incr ( 1'b0 ) ,
.decr ( bxfer ) ,
.load_value ( num_transactions ) ,
.count ( b_transactions_to_go ) ,
.is_zero ( b_final_transaction )
);
endmodule : krnl_axi_write_master
`default_nettype wire

437
hw/afu/xrt/krnl_control_s_axi.v
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@ -1,437 +0,0 @@
/**
* Copyright (C) 2019-2021 Xilinx, Inc
*
* Licensed under the Apache License, Version 2.0 (the "License"). You may
* not use this file except in compliance with the License. A copy of the
* License is located at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*/
`timescale 1ns/1ps
module krnl_control_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 6,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
// user signals
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle,
output wire [63:0] a,
output wire [63:0] b,
output wire [63:0] c,
output wire [31:0] length_r
);
//------------------------Address Info-------------------
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : Data signal of a
// bit 31~0 - a[31:0] (Read/Write)
// 0x14 : Data signal of a
// bit 31~0 - a[63:32] (Read/Write)
// 0x18 : reserved
// 0x1c : Data signal of b
// bit 31~0 - b[31:0] (Read/Write)
// 0x20 : Data signal of b
// bit 31~0 - b[63:32] (Read/Write)
// 0x24 : reserved
// 0x28 : Data signal of c
// bit 31~0 - c[31:0] (Read/Write)
// 0x2c : Data signal of c
// bit 31~0 - c[63:32] (Read/Write)
// 0x30 : reserved
// 0x34 : Data signal of length_r
// bit 31~0 - length_r[31:0] (Read/Write)
// 0x38 : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_AP_CTRL = 6'h00,
ADDR_GIE = 6'h04,
ADDR_IER = 6'h08,
ADDR_ISR = 6'h0c,
ADDR_A_DATA_0 = 6'h10,
ADDR_A_DATA_1 = 6'h14,
ADDR_A_CTRL = 6'h18,
ADDR_B_DATA_0 = 6'h1c,
ADDR_B_DATA_1 = 6'h20,
ADDR_B_CTRL = 6'h24,
ADDR_C_DATA_0 = 6'h28,
ADDR_C_DATA_1 = 6'h2c,
ADDR_C_CTRL = 6'h30,
ADDR_LENGTH_R_DATA_0 = 6'h34,
ADDR_LENGTH_R_CTRL = 6'h38,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
RDIDLE = 2'd0,
RDDATA = 2'd1,
ADDR_BITS = 6;
//------------------------Local signal-------------------
reg [1:0] wstate = WRIDLE;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate = RDIDLE;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
wire int_ap_idle;
wire int_ap_ready;
reg int_ap_done = 1'b0;
reg int_ap_start = 1'b0;
reg int_auto_restart = 1'b0;
reg int_gie = 2'b0;
reg [1:0] int_ier = 2'b0;
reg [1:0] int_isr = 2'b0;
reg [63:0] int_a = 64'b0;
reg [63:0] int_b = 64'b0;
reg [63:0] int_c = 64'b0;
reg [31:0] int_length_r = 32'b0;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (~ARESET) & (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRIDLE;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (~ARESET) && (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDIDLE;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
ADDR_A_DATA_0: begin
rdata <= int_a[31:0];
end
ADDR_A_DATA_1: begin
rdata <= int_a[63:32];
end
ADDR_B_DATA_0: begin
rdata <= int_b[31:0];
end
ADDR_B_DATA_1: begin
rdata <= int_b[63:32];
end
ADDR_C_DATA_0: begin
rdata <= int_c[31:0];
end
ADDR_C_DATA_1: begin
rdata <= int_c[63:32];
end
ADDR_LENGTH_R_DATA_0: begin
rdata <= int_length_r[31:0];
end
endcase
end
end
end
//------------------------Register logic-----------------
assign interrupt = int_gie & (|int_isr);
assign ap_start = int_ap_start;
assign int_ap_idle = ap_idle;
assign int_ap_ready = ap_ready;
assign a = int_a;
assign b = int_b;
assign c = int_c;
assign length_r = int_length_r;
// int_ap_start
always @(posedge ACLK) begin
if (ARESET)
int_ap_start <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
int_ap_start <= 1'b1;
else if (int_ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
end
// int_ap_done
always @(posedge ACLK) begin
if (ARESET)
int_ap_done <= 1'b0;
else if (ACLK_EN) begin
if (ap_done)
int_ap_done <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
int_ap_done <= 1'b0; // clear on read
end
end
// int_auto_restart
always @(posedge ACLK) begin
if (ARESET)
int_auto_restart <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
int_auto_restart <= WDATA[7];
end
end
// int_gie
always @(posedge ACLK) begin
if (ARESET)
int_gie <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_GIE && WSTRB[0])
int_gie <= WDATA[0];
end
end
// int_ier
always @(posedge ACLK) begin
if (ARESET)
int_ier <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[1:0];
end
end
// int_isr[0]
always @(posedge ACLK) begin
if (ARESET)
int_isr[0] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
end
end
// int_isr[1]
always @(posedge ACLK) begin
if (ARESET)
int_isr[1] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
end
end
// int_a[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_a[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_A_DATA_0)
int_a[31:0] <= (WDATA[31:0] & wmask) | (int_a[31:0] & ~wmask);
end
end
// int_a[63:32]
always @(posedge ACLK) begin
if (ARESET)
int_a[63:32] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_A_DATA_1)
int_a[63:32] <= (WDATA[31:0] & wmask) | (int_a[63:32] & ~wmask);
end
end
// int_b[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_b[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_B_DATA_0)
int_b[31:0] <= (WDATA[31:0] & wmask) | (int_b[31:0] & ~wmask);
end
end
// int_b[63:32]
always @(posedge ACLK) begin
if (ARESET)
int_b[63:32] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_B_DATA_1)
int_b[63:32] <= (WDATA[31:0] & wmask) | (int_b[63:32] & ~wmask);
end
end
// int_c[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_c[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_C_DATA_0)
int_c[31:0] <= (WDATA[31:0] & wmask) | (int_c[31:0] & ~wmask);
end
end
// int_c[63:32]
always @(posedge ACLK) begin
if (ARESET)
int_c[63:32] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_C_DATA_1)
int_c[63:32] <= (WDATA[31:0] & wmask) | (int_c[63:32] & ~wmask);
end
end
// int_length_r[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_length_r[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_LENGTH_R_DATA_0)
int_length_r[31:0] <= (WDATA[31:0] & wmask) | (int_length_r[31:0] & ~wmask);
end
end
//------------------------Memory logic-------------------
endmodule

87
hw/afu/xrt/krnl_vadd_rtl_counter.sv
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@ -1,87 +0,0 @@
/**
* Copyright (C) 2019-2021 Xilinx, Inc
*
* Licensed under the Apache License, Version 2.0 (the "License"). You may
* not use this file except in compliance with the License. A copy of the
* License is located at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*/
//-----------------------------------------------------------------------------
// Simple up/down counter with reset.
//-----------------------------------------------------------------------------
`default_nettype none
`timescale 1ps/1ps
module krnl_counter #(
parameter integer C_WIDTH = 4,
parameter [C_WIDTH-1:0] C_INIT = {C_WIDTH{1'b0}}
)
(
input wire clk,
input wire clken,
input wire rst,
input wire load,
input wire incr,
input wire decr,
input wire [C_WIDTH-1:0] load_value,
output wire [C_WIDTH-1:0] count,
output wire is_zero
);
localparam [C_WIDTH-1:0] LP_ZERO = {C_WIDTH{1'b0}};
localparam [C_WIDTH-1:0] LP_ONE = {{C_WIDTH-1{1'b0}},1'b1};
localparam [C_WIDTH-1:0] LP_MAX = {C_WIDTH{1'b1}};
reg [C_WIDTH-1:0] count_r = C_INIT;
reg is_zero_r = (C_INIT == LP_ZERO);
assign count = count_r;
always @(posedge clk) begin
if (rst) begin
count_r <= C_INIT;
end
else if (clken) begin
if (load) begin
count_r <= load_value;
end
else if (incr & ~decr) begin
count_r <= count_r + 1'b1;
end
else if (~incr & decr) begin
count_r <= count_r - 1'b1;
end
else
count_r <= count_r;
end
end
assign is_zero = is_zero_r;
always @(posedge clk) begin
if (rst) begin
is_zero_r <= (C_INIT == LP_ZERO);
end
else if (clken) begin
if (load) begin
is_zero_r <= (load_value == LP_ZERO);
end
else begin
is_zero_r <= incr ^ decr ? (decr && (count_r == LP_ONE)) || (incr && (count_r == LP_MAX)) : is_zero_r;
end
end
else begin
is_zero_r <= is_zero_r;
end
end
endmodule : krnl_counter
`default_nettype wire

616
hw/afu/xrt/vortex_afu.v
View file

@ -1,437 +1,229 @@
`include "VX_define.vh"
module vortex_afu #(
parameter AXI_DATA_WIDTH = `VX_MEM_DATA_WIDTH,
parameter AXI_ADDR_WIDTH = `VX_MEM_ADDR_WIDTH,
parameter AXI_TID_WIDTH = 12,
parameter AXI_STROBE_WIDTH = `VX_MEM_BYTEEN_WIDTH,
parameter AXI_DCR_ADDR_WIDTH = `VX_DCR_ADDR_WIDTH,
parameter AXI_DCR_DATA_WIDTH = `VX_DCR_DATA_WIDTH
parameter C_S_AXI_CONTROL_DATA_WIDTH = 32,
parameter C_S_AXI_CONTROL_ADDR_WIDTH = 6,
parameter C_M_AXI_GMEM_ID_WIDTH = 10,
parameter C_M_AXI_GMEM_ADDR_WIDTH = `VX_MEM_ADDR_WIDTH,
parameter C_M_AXI_GMEM_DATA_WIDTH = `VX_MEM_DATA_WIDTH
) (
// System signals
input wire ap_clk,
input wire ap_rst_n,
input wire ap_clk,
input wire ap_rst_n,
// AXI4 master interface
output wire m_axi_gmem_AWVALID,
input wire m_axi_gmem_AWREADY,
output wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0] m_axi_gmem_AWADDR,
output wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_gmem_AWID,
output wire [7:0] m_axi_gmem_AWLEN,
output wire [2:0] m_axi_gmem_AWSIZE,
// Tie-off AXI4 transaction options that are not being used.
output wire [1:0] m_axi_gmem_AWBURST,
output wire [1:0] m_axi_gmem_AWLOCK,
output wire [3:0] m_axi_gmem_AWCACHE,
output wire [2:0] m_axi_gmem_AWPROT,
output wire [3:0] m_axi_gmem_AWQOS,
output wire [3:0] m_axi_gmem_AWREGION,
output wire m_axi_gmem_WVALID,
input wire m_axi_gmem_WREADY,
output wire [C_M_AXI_GMEM_DATA_WIDTH-1:0] m_axi_gmem_WDATA,
output wire [C_M_AXI_GMEM_DATA_WIDTH/8-1:0] m_axi_gmem_WSTRB,
output wire m_axi_gmem_WLAST,
output wire m_axi_gmem_ARVALID,
input wire m_axi_gmem_ARREADY,
output wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0] m_axi_gmem_ARADDR,
output wire [C_M_AXI_GMEM_ID_WIDTH-1:0] m_axi_gmem_ARID,
output wire [7:0] m_axi_gmem_ARLEN,
output wire [2:0] m_axi_gmem_ARSIZE,
output wire [1:0] m_axi_gmem_ARBURST,
output wire [1:0] m_axi_gmem_ARLOCK,
output wire [3:0] m_axi_gmem_ARCACHE,
output wire [2:0] m_axi_gmem_ARPROT,
output wire [3:0] m_axi_gmem_ARQOS,
output wire [3:0] m_axi_gmem_ARREGION,
input wire m_axi_gmem_RVALID,
output wire m_axi_gmem_RREADY,
input wire [C_M_AXI_GMEM_DATA_WIDTH - 1:0] m_axi_gmem_RDATA,
input wire m_axi_gmem_RLAST,
input wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_gmem_RID,
input wire [1:0] m_axi_gmem_RRESP,
input wire m_axi_gmem_BVALID,
output wire m_axi_gmem_BREADY,
input wire [1:0] m_axi_gmem_BRESP,
input wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_gmem_BID,
// AXI4 memory interface
output wire m_axi_gmem_awvalid,
input wire m_axi_gmem_awready,
output wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0] m_axi_gmem_awaddr,
output wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_gmem_awid,
output wire [7:0] m_axi_gmem_awlen,
output wire [2:0] m_axi_gmem_awsize,
output wire [1:0] m_axi_gmem_awburst,
output wire [1:0] m_axi_gmem_awlock,
output wire [3:0] m_axi_gmem_awcache,
output wire [2:0] m_axi_gmem_awprot,
output wire [3:0] m_axi_gmem_awqos,
output wire [3:0] m_axi_gmem_awregion,
output wire m_axi_gmem_wvalid,
input wire m_axi_gmem_wready,
output wire [C_M_AXI_GMEM_DATA_WIDTH-1:0] m_axi_gmem_wdata,
output wire [C_M_AXI_GMEM_DATA_WIDTH/8-1:0] m_axi_gmem_wstrb,
output wire m_axi_gmem_wlast,
output wire m_axi_gmem_arvalid,
input wire m_axi_gmem_arready,
output wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0] m_axi_gmem_araddr,
output wire [C_M_AXI_GMEM_ID_WIDTH-1:0] m_axi_gmem_arid,
output wire [7:0] m_axi_gmem_arlen,
output wire [2:0] m_axi_gmem_arsize,
output wire [1:0] m_axi_gmem_arburst,
output wire [1:0] m_axi_gmem_arlock,
output wire [3:0] m_axi_gmem_arcache,
output wire [2:0] m_axi_gmem_arprot,
output wire [3:0] m_axi_gmem_arqos,
output wire [3:0] m_axi_gmem_arregion,
input wire m_axi_gmem_rvalid,
output wire m_axi_gmem_rready,
input wire [C_M_AXI_GMEM_DATA_WIDTH - 1:0] m_axi_gmem_rdata,
input wire m_axi_gmem_rlast,
input wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_gmem_rid,
input wire [1:0] m_axi_gmem_rresp,
input wire m_axi_gmem_bvalid,
output wire m_axi_gmem_bready,
input wire [1:0] m_axi_gmem_bresp,
input wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_gmem_bid,
// AXI4-Lite slave interface
input wire s_axi_control_AWVALID,
output wire s_axi_control_AWREADY,
input wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_AWADDR,
input wire s_axi_control_WVALID,
output wire s_axi_control_WREADY,
input wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_WDATA,
input wire [C_S_AXI_CONTROL_DATA_WIDTH/8-1:0] s_axi_control_WSTRB,
input wire s_axi_control_ARVALID,
output wire s_axi_control_ARREADY,
input wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_ARADDR,
output wire s_axi_control_RVALID,
input wire s_axi_control_RREADY,
output wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_RDATA,
output wire [1:0] s_axi_control_RRESP,
output wire s_axi_control_BVALID,
input wire s_axi_control_BREADY,
output wire [1:0] s_axi_control_BRESP
// AXI4-Lite control interface
input wire s_axi_control_awvalid,
output wire s_axi_control_awready,
input wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_awaddr,
input wire s_axi_control_wvalid,
output wire s_axi_control_wready,
input wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_wdata,
input wire [C_S_AXI_CONTROL_DATA_WIDTH/8-1:0] s_axi_control_wstrb,
input wire s_axi_control_arvalid,
output wire s_axi_control_arready,
input wire [C_S_AXI_CONTROL_ADDR_WIDTH-1:0] s_axi_control_araddr,
output wire s_axi_control_rvalid,
input wire s_axi_control_rready,
output wire [C_S_AXI_CONTROL_DATA_WIDTH-1:0] s_axi_control_rdata,
output wire [1:0] s_axi_control_rresp,
output wire s_axi_control_bvalid,
input wire s_axi_control_bready,
output wire [1:0] s_axi_control_bresp,
output wire interrupt
);
///////////////////////////////////////////////////////////////////////////////
// Local Parameters (constants)
///////////////////////////////////////////////////////////////////////////////
localparam integer LP_NUM_READ_CHANNELS = 2;
localparam integer LP_LENGTH_WIDTH = 32;
localparam integer LP_DW_BYTES = C_M_AXI_GMEM_DATA_WIDTH/8;
localparam integer LP_AXI_BURST_LEN = 4096/LP_DW_BYTES < 256 ? 4096/LP_DW_BYTES : 256;
localparam integer LP_LOG_BURST_LEN = $clog2(LP_AXI_BURST_LEN);
localparam integer LP_RD_MAX_OUTSTANDING = 3;
localparam integer LP_RD_FIFO_DEPTH = LP_AXI_BURST_LEN*(LP_RD_MAX_OUTSTANDING + 1);
localparam integer LP_WR_FIFO_DEPTH = LP_AXI_BURST_LEN;
`STATIC_ASSERT((C_M_AXI_GMEM_ID_WIDTH == `VX_MEM_TAG_WIDTH), ("invalid memory tag size: current=%0d, expected=%0d", C_M_AXI_GMEM_ID_WIDTH, `VX_MEM_TAG_WIDTH))
///////////////////////////////////////////////////////////////////////////////
// Variables
///////////////////////////////////////////////////////////////////////////////
logic areset = 1'b0;
logic ap_start;
logic ap_start_pulse;
logic ap_start_r;
logic ap_ready;
logic ap_done;
logic ap_idle = 1'b1;
logic [C_M_AXI_GMEM_ADDR_WIDTH-1:0] a;
logic [C_M_AXI_GMEM_ADDR_WIDTH-1:0] b;
logic [C_M_AXI_GMEM_ADDR_WIDTH-1:0] c;
logic [LP_LENGTH_WIDTH-1:0] length_r;
logic read_done;
logic [LP_NUM_READ_CHANNELS-1:0] rd_tvalid;
logic [LP_NUM_READ_CHANNELS-1:0] rd_tready_n;
logic [LP_NUM_READ_CHANNELS-1:0] [C_M_AXI_GMEM_DATA_WIDTH-1:0] rd_tdata;
logic [LP_NUM_READ_CHANNELS-1:0] ctrl_rd_fifo_prog_full;
logic [LP_NUM_READ_CHANNELS-1:0] rd_fifo_tvalid_n;
logic [LP_NUM_READ_CHANNELS-1:0] rd_fifo_tready;
logic [LP_NUM_READ_CHANNELS-1:0] [C_M_AXI_GMEM_DATA_WIDTH-1:0] rd_fifo_tdata;
logic adder_tvalid;
logic adder_tready_n;
logic [C_M_AXI_GMEM_DATA_WIDTH-1:0] adder_tdata;
logic wr_fifo_tvalid_n;
logic wr_fifo_tready;
logic [C_M_AXI_GMEM_DATA_WIDTH-1:0] wr_fifo_tdata;
///////////////////////////////////////////////////////////////////////////////
// RTL Logic
///////////////////////////////////////////////////////////////////////////////
// Tie-off unused AXI protocol features
assign m_axi_gmem_AWID = {C_M_AXI_GMEM_ID_WIDTH{1'b0}};
assign m_axi_gmem_AWBURST = 2'b01;
assign m_axi_gmem_AWLOCK = 2'b00;
assign m_axi_gmem_AWCACHE = 4'b0011;
assign m_axi_gmem_AWPROT = 3'b000;
assign m_axi_gmem_AWQOS = 4'b0000;
assign m_axi_gmem_AWREGION = 4'b0000;
assign m_axi_gmem_ARBURST = 2'b01;
assign m_axi_gmem_ARLOCK = 2'b00;
assign m_axi_gmem_ARCACHE = 4'b0011;
assign m_axi_gmem_ARPROT = 3'b000;
assign m_axi_gmem_ARQOS = 4'b0000;
assign m_axi_gmem_ARREGION = 4'b0000;
// Register and invert reset signal for better timing.
always @(posedge ap_clk) begin
areset <= ~ap_rst_n;
// Register and invert reset signal.
reg reset;
always @(posedge ap_clk) begin
reset <= ~ap_rst_n;
end
// create pulse when ap_start transitions to 1
always @(posedge ap_clk) begin
begin
ap_start_r <= ap_start;
end
reg vx_reset;
wire vx_busy;
wire dcr_wr_valid;
wire [`VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr;
wire [`VX_DCR_DATA_WIDTH-1:0] dcr_wr_data;
wire ap_start;
wire ap_idle = ~vx_busy;
wire ap_done = ap_idle;
wire ap_ready = ap_idle;
reg [$clog2(`RESET_DELAY+1)-1:0] vx_reset_ctr;
reg vx_running;
always @(posedge ap_clk) begin
if (~vx_running && vx_reset == 0 && ap_start) begin
vx_reset_ctr <= 0;
end else begin
vx_reset_ctr <= vx_reset_ctr + 1;
end
end
assign ap_start_pulse = ap_start & ~ap_start_r;
// ap_idle is asserted when done is asserted, it is de-asserted when ap_start_pulse
// is asserted
always @(posedge ap_clk) begin
if (areset) begin
ap_idle <= 1'b1;
end
else begin
ap_idle <= ap_done ? 1'b1 :
ap_start_pulse ? 1'b0 :
ap_idle;
end
always @(posedge ap_clk) begin
if (reset) begin
vx_reset <= 0;
vx_running <= 0;
end else begin
if (vx_running) begin
if (~vx_busy) begin
vx_running <= 0;
end
end else begin
if (vx_reset == 0 && ap_start) begin
vx_reset <= 1;
end
if (vx_reset_ctr == (`RESET_DELAY-1)) begin
vx_running <= 1;
vx_reset <= 0;
end
end
end
end
assign ap_ready = ap_done;
VX_afu_control #(
.AXI_ADDR_WIDTH (C_S_AXI_CONTROL_ADDR_WIDTH),
.AXI_DATA_WIDTH (C_S_AXI_CONTROL_DATA_WIDTH)
) afu_control (
.clk (ap_clk),
.reset (reset),
.clk_en (1'b1),
.s_axi_awvalid (s_axi_control_awvalid),
.s_axi_awready (s_axi_control_awready),
.s_axi_awaddr (s_axi_control_awaddr),
.s_axi_wvalid (s_axi_control_wvalid),
.s_axi_wready (s_axi_control_wready),
.s_axi_wdata (s_axi_control_wdata),
.s_axi_wstrb (s_axi_control_wstrb),
.s_axi_arvalid (s_axi_control_arvalid),
.s_axi_arready (s_axi_control_arready),
.s_axi_araddr (s_axi_control_araddr),
.s_axi_rvalid (s_axi_control_rvalid),
.s_axi_rready (s_axi_control_rready),
.s_axi_rdata (s_axi_control_rdata),
.s_axi_rresp (s_axi_control_rresp),
.s_axi_bvalid (s_axi_control_bvalid),
.s_axi_bready (s_axi_control_bready),
.s_axi_bresp (s_axi_control_bresp),
// AXI4-Lite slave
krnl_vadd_rtl_control_s_axi #(
.C_S_AXI_ADDR_WIDTH( C_S_AXI_CONTROL_ADDR_WIDTH ),
.C_S_AXI_DATA_WIDTH( C_S_AXI_CONTROL_DATA_WIDTH )
)
inst_krnl_vadd_control_s_axi (
.AWVALID ( s_axi_control_AWVALID ) ,
.AWREADY ( s_axi_control_AWREADY ) ,
.AWADDR ( s_axi_control_AWADDR ) ,
.WVALID ( s_axi_control_WVALID ) ,
.WREADY ( s_axi_control_WREADY ) ,
.WDATA ( s_axi_control_WDATA ) ,
.WSTRB ( s_axi_control_WSTRB ) ,
.ARVALID ( s_axi_control_ARVALID ) ,
.ARREADY ( s_axi_control_ARREADY ) ,
.ARADDR ( s_axi_control_ARADDR ) ,
.RVALID ( s_axi_control_RVALID ) ,
.RREADY ( s_axi_control_RREADY ) ,
.RDATA ( s_axi_control_RDATA ) ,
.RRESP ( s_axi_control_RRESP ) ,
.BVALID ( s_axi_control_BVALID ) ,
.BREADY ( s_axi_control_BREADY ) ,
.BRESP ( s_axi_control_BRESP ) ,
.ACLK ( ap_clk ) ,
.ARESET ( areset ) ,
.ACLK_EN ( 1'b1 ) ,
.ap_start ( ap_start ) ,
.interrupt ( interrupt ) ,
.ap_ready ( ap_ready ) ,
.ap_done ( ap_done ) ,
.ap_idle ( ap_idle ) ,
.a ( a[0+:C_M_AXI_GMEM_ADDR_WIDTH] ) ,
.b ( b[0+:C_M_AXI_GMEM_ADDR_WIDTH] ) ,
.c ( c[0+:C_M_AXI_GMEM_ADDR_WIDTH] ) ,
.length_r ( length_r[0+:LP_LENGTH_WIDTH] )
.ap_start (ap_start),
.ap_done (ap_done),
.ap_ready (ap_ready),
.ap_idle (ap_idle),
.interrupt (interrupt),
.dcr_wr_valid (dcr_wr_valid),
.dcr_wr_addr (dcr_wr_addr),
.dcr_wr_data (dcr_wr_data)
);
// AXI4 Read Master
krnl_vadd_rtl_axi_read_master #(
.C_ADDR_WIDTH ( C_M_AXI_GMEM_ADDR_WIDTH ) ,
.C_DATA_WIDTH ( C_M_AXI_GMEM_DATA_WIDTH ) ,
.C_ID_WIDTH ( C_M_AXI_GMEM_ID_WIDTH ) ,
.C_NUM_CHANNELS ( LP_NUM_READ_CHANNELS ) ,
.C_LENGTH_WIDTH ( LP_LENGTH_WIDTH ) ,
.C_BURST_LEN ( LP_AXI_BURST_LEN ) ,
.C_LOG_BURST_LEN ( LP_LOG_BURST_LEN ) ,
.C_MAX_OUTSTANDING ( LP_RD_MAX_OUTSTANDING )
)
inst_axi_read_master (
.aclk ( ap_clk ) ,
.areset ( areset ) ,
wire m_axi_gmem_awvalid_unqual;
wire m_axi_gmem_wvalid_unqual;
wire m_axi_gmem_arvalid_unqual;
.ctrl_start ( ap_start_pulse ) ,
.ctrl_done ( read_done ) ,
.ctrl_offset ( {b,a} ) ,
.ctrl_length ( length_r ) ,
.ctrl_prog_full ( ctrl_rd_fifo_prog_full ) ,
.arvalid ( m_axi_gmem_ARVALID ) ,
.arready ( m_axi_gmem_ARREADY ) ,
.araddr ( m_axi_gmem_ARADDR ) ,
.arid ( m_axi_gmem_ARID ) ,
.arlen ( m_axi_gmem_ARLEN ) ,
.arsize ( m_axi_gmem_ARSIZE ) ,
.rvalid ( m_axi_gmem_RVALID ) ,
.rready ( m_axi_gmem_RREADY ) ,
.rdata ( m_axi_gmem_RDATA ) ,
.rlast ( m_axi_gmem_RLAST ) ,
.rid ( m_axi_gmem_RID ) ,
.rresp ( m_axi_gmem_RRESP ) ,
.m_tvalid ( rd_tvalid ) ,
.m_tready ( ~rd_tready_n ) ,
.m_tdata ( rd_tdata )
);
// xpm_fifo_sync: Synchronous FIFO
// Xilinx Parameterized Macro, Version 2016.4
xpm_fifo_sync # (
.FIFO_MEMORY_TYPE ("auto"), //string; "auto", "block", "distributed", or "ultra";
.ECC_MODE ("no_ecc"), //string; "no_ecc" or "en_ecc";
.FIFO_WRITE_DEPTH (LP_RD_FIFO_DEPTH), //positive integer
.WRITE_DATA_WIDTH (C_M_AXI_GMEM_DATA_WIDTH), //positive integer
.WR_DATA_COUNT_WIDTH ($clog2(LP_RD_FIFO_DEPTH)+1), //positive integer, Not used
.PROG_FULL_THRESH (LP_AXI_BURST_LEN-2), //positive integer
.FULL_RESET_VALUE (1), //positive integer; 0 or 1
.READ_MODE ("fwft"), //string; "std" or "fwft";
.FIFO_READ_LATENCY (1), //positive integer;
.READ_DATA_WIDTH (C_M_AXI_GMEM_DATA_WIDTH), //positive integer
.RD_DATA_COUNT_WIDTH ($clog2(LP_RD_FIFO_DEPTH)+1), //positive integer, not used
.PROG_EMPTY_THRESH (10), //positive integer, not used
.DOUT_RESET_VALUE ("0"), //string, don't care
.WAKEUP_TIME (0) //positive integer; 0 or 2;
) inst_rd_xpm_fifo_sync[LP_NUM_READ_CHANNELS-1:0] (
.sleep ( 1'b0 ) ,
.rst ( areset ) ,
.wr_clk ( ap_clk ) ,
.wr_en ( rd_tvalid ) ,
.din ( rd_tdata ) ,
.full ( rd_tready_n ) ,
.prog_full ( ctrl_rd_fifo_prog_full) ,
.wr_data_count ( ) ,
.overflow ( ) ,
.wr_rst_busy ( ) ,
.rd_en ( rd_fifo_tready ) ,
.dout ( rd_fifo_tdata ) ,
.empty ( rd_fifo_tvalid_n ) ,
.prog_empty ( ) ,
.rd_data_count ( ) ,
.underflow ( ) ,
.rd_rst_busy ( ) ,
.injectsbiterr ( 1'b0 ) ,
.injectdbiterr ( 1'b0 ) ,
.sbiterr ( ) ,
.dbiterr ( )
);
// Combinatorial Adder
krnl_vadd_rtl_adder #(
.C_DATA_WIDTH ( C_M_AXI_GMEM_DATA_WIDTH ) ,
.C_NUM_CHANNELS ( LP_NUM_READ_CHANNELS )
)
inst_adder (
.aclk ( ap_clk ) ,
.areset ( areset ) ,
.s_tvalid ( ~rd_fifo_tvalid_n ) ,
.s_tready ( rd_fifo_tready ) ,
.s_tdata ( rd_fifo_tdata ) ,
.m_tvalid ( adder_tvalid ) ,
.m_tready ( ~adder_tready_n ) ,
.m_tdata ( adder_tdata )
);
// xpm_fifo_sync: Synchronous FIFO
// Xilinx Parameterized Macro, Version 2016.4
xpm_fifo_sync # (
.FIFO_MEMORY_TYPE ("auto"), //string; "auto", "block", "distributed", or "ultra";
.ECC_MODE ("no_ecc"), //string; "no_ecc" or "en_ecc";
.FIFO_WRITE_DEPTH (LP_WR_FIFO_DEPTH), //positive integer
.WRITE_DATA_WIDTH (C_M_AXI_GMEM_DATA_WIDTH), //positive integer
.WR_DATA_COUNT_WIDTH ($clog2(LP_WR_FIFO_DEPTH)), //positive integer, Not used
.PROG_FULL_THRESH (10), //positive integer, Not used
.FULL_RESET_VALUE (1), //positive integer; 0 or 1
.READ_MODE ("fwft"), //string; "std" or "fwft";
.FIFO_READ_LATENCY (1), //positive integer;
.READ_DATA_WIDTH (C_M_AXI_GMEM_DATA_WIDTH), //positive integer
.RD_DATA_COUNT_WIDTH ($clog2(LP_WR_FIFO_DEPTH)), //positive integer, not used
.PROG_EMPTY_THRESH (10), //positive integer, not used
.DOUT_RESET_VALUE ("0"), //string, don't care
.WAKEUP_TIME (0) //positive integer; 0 or 2;
) inst_wr_xpm_fifo_sync (
.sleep ( 1'b0 ) ,
.rst ( areset ) ,
.wr_clk ( ap_clk ) ,
.wr_en ( adder_tvalid ) ,
.din ( adder_tdata ) ,
.full ( adder_tready_n ) ,
.prog_full ( ) ,
.wr_data_count ( ) ,
.overflow ( ) ,
.wr_rst_busy ( ) ,
.rd_en ( wr_fifo_tready ) ,
.dout ( wr_fifo_tdata ) ,
.empty ( wr_fifo_tvalid_n ) ,
.prog_empty ( ) ,
.rd_data_count ( ) ,
.underflow ( ) ,
.rd_rst_busy ( ) ,
.injectsbiterr ( 1'b0 ) ,
.injectdbiterr ( 1'b0 ) ,
.sbiterr ( ) ,
.dbiterr ( )
);
// AXI4 Write Master
krnl_vadd_rtl_axi_write_master #(
.C_ADDR_WIDTH ( C_M_AXI_GMEM_ADDR_WIDTH ) ,
.C_DATA_WIDTH ( C_M_AXI_GMEM_DATA_WIDTH ) ,
.C_MAX_LENGTH_WIDTH ( LP_LENGTH_WIDTH ) ,
.C_BURST_LEN ( LP_AXI_BURST_LEN ) ,
.C_LOG_BURST_LEN ( LP_LOG_BURST_LEN )
)
inst_axi_write_master (
.aclk ( ap_clk ) ,
.areset ( areset ) ,
.ctrl_start ( ap_start_pulse ) ,
.ctrl_offset ( c ) ,
.ctrl_length ( length_r ) ,
.ctrl_done ( ap_done ) ,
.awvalid ( m_axi_gmem_AWVALID ) ,
.awready ( m_axi_gmem_AWREADY ) ,
.awaddr ( m_axi_gmem_AWADDR ) ,
.awlen ( m_axi_gmem_AWLEN ) ,
.awsize ( m_axi_gmem_AWSIZE ) ,
.s_tvalid ( ~wr_fifo_tvalid_n ) ,
.s_tready ( wr_fifo_tready ) ,
.s_tdata ( wr_fifo_tdata ) ,
.wvalid ( m_axi_gmem_WVALID ) ,
.wready ( m_axi_gmem_WREADY ) ,
.wdata ( m_axi_gmem_WDATA ) ,
.wstrb ( m_axi_gmem_WSTRB ) ,
.wlast ( m_axi_gmem_WLAST ) ,
.bvalid ( m_axi_gmem_BVALID ) ,
.bready ( m_axi_gmem_BREADY ) ,
.bresp ( m_axi_gmem_BRESP )
);
assign m_axi_gmem_awvalid = m_axi_gmem_awvalid_unqual && vx_running;
assign m_axi_gmem_wvalid = m_axi_gmem_wvalid_unqual && vx_running;
assign m_axi_gmem_arvalid = m_axi_gmem_arvalid_unqual && vx_running;
Vortex_axi #(
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_TID_WIDTH (AXI_TID_WIDTH),
.AXI_STROBE_WIDTH (AXI_STROBE_WIDTH),
.AXI_DCR_ADDR_WIDTH (AXI_DCR_ADDR_WIDTH),
.AXI_DCR_DATA_WIDTH (AXI_DCR_DATA_WIDTH)
) inst (
.clk(clk),
.reset(reset),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready),
.busy(busy)
.AXI_DATA_WIDTH (C_M_AXI_GMEM_DATA_WIDTH),
.AXI_ADDR_WIDTH (C_M_AXI_GMEM_ADDR_WIDTH),
.AXI_TID_WIDTH (C_M_AXI_GMEM_ID_WIDTH)
) vortex_axi (
.clk (ap_clk),
.reset (reset || vx_reset),
.m_axi_awid (m_axi_gmem_awid),
.m_axi_awaddr (m_axi_gmem_awaddr),
.m_axi_awlen (m_axi_gmem_awlen),
.m_axi_awsize (m_axi_gmem_awsize),
.m_axi_awburst (m_axi_gmem_awburst),
.m_axi_awlock (m_axi_gmem_awlock),
.m_axi_awcache (m_axi_gmem_awcache),
.m_axi_awprot (m_axi_gmem_awprot),
.m_axi_awqos (m_axi_gmem_awqos),
.m_axi_awregion (m_axi_gmem_awregion),
.m_axi_awvalid (m_axi_gmem_awvalid_unqual),
.m_axi_awready (m_axi_gmem_awready),
.m_axi_wdata (m_axi_gmem_wdata),
.m_axi_wstrb (m_axi_gmem_wstrb),
.m_axi_wlast (m_axi_gmem_wlast),
.m_axi_wvalid (m_axi_gmem_wvalid_unqual),
.m_axi_wready (m_axi_gmem_wready),
.m_axi_bid (m_axi_gmem_bid),
.m_axi_bresp (m_axi_gmem_bresp),
.m_axi_bvalid (m_axi_gmem_bvalid),
.m_axi_bready (m_axi_gmem_bready),
.m_axi_arid (m_axi_gmem_arid),
.m_axi_araddr (m_axi_gmem_araddr),
.m_axi_arlen (m_axi_gmem_arlen),
.m_axi_arsize (m_axi_gmem_arsize),
.m_axi_arburst (m_axi_gmem_arburst),
.m_axi_arlock (m_axi_gmem_arlock),
.m_axi_arcache (m_axi_gmem_arcache),
.m_axi_arprot (m_axi_gmem_arprot),
.m_axi_arqos (m_axi_gmem_arqos),
.m_axi_arregion (m_axi_gmem_arregion),
.m_axi_arvalid (m_axi_gmem_arvalid_unqual),
.m_axi_arready (m_axi_gmem_arready),
.m_axi_rid (m_axi_gmem_rid),
.m_axi_rdata (m_axi_gmem_rdata),
.m_axi_rresp (m_axi_gmem_rresp),
.m_axi_rlast (m_axi_gmem_rlast),
.m_axi_rvalid (m_axi_gmem_rvalid),
.m_axi_rready (m_axi_gmem_rready),
.dcr_wr_valid (dcr_wr_valid),
.dcr_wr_addr (dcr_wr_addr),
.dcr_wr_data (dcr_wr_data),
.busy (vx_busy)
);
endmodule

0
hw/ip/altera/arria10/VX_acl_fdiv.sv → hw/ip/altera/VX_acl_fdiv.sv
View file

0
hw/ip/altera/arria10/VX_acl_fma.sv → hw/ip/altera/VX_acl_fma.sv
View file

0
hw/ip/altera/arria10/VX_acl_fsqrt.sv → hw/ip/altera/VX_acl_fsqrt.sv
View file

62
hw/ip/altera/stratix10/VX_acl_fdiv.sv
View file

@ -1,62 +0,0 @@
`include "VX_fpu_define.vh"
module VX_acl_fdiv #(
parameter NUM_LANES = 1,
parameter TAGW = 1,
parameter LATENCY = 34
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [TAGW-1:0] tag_in,
input wire [`INST_FRM_BITS-1:0] frm,
input wire [NUM_LANES-1:0][31:0] dataa,
input wire [NUM_LANES-1:0][31:0] datab,
output wire [NUM_LANES-1:0][31:0] result,
output wire has_fflags,
output fflags_t [NUM_LANES-1:0] fflags,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
);
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
for (genvar i = 0; i < NUM_LANES; ++i) begin
acl_fdiv fdiv (
.clk (clk),
.areset (1'b0),
.en (enable),
.a (dataa[i]),
.b (datab[i]),
.q (result[i])
);
end
VX_shift_register #(
.DATAW (1 + TAGW),
.DEPTH (LATENCY),
.RESETW (1)
) shift_reg (
.clk (clk),
.reset (reset),
.enable (enable),
.data_in ({valid_in, tag_in}),
.data_out ({valid_out, tag_out})
);
assign ready_in = enable;
`UNUSED_VAR (frm)
assign has_fflags = 0;
assign fflags = 0;
endmodule

92
hw/ip/altera/stratix10/VX_acl_fma.sv
View file

@ -1,92 +0,0 @@
`include "VX_fpu_define.vh"
module VX_acl_fma #(
parameter NUM_LANES = 1,
parameter TAGW = 1,
parameter LATENCY = 4
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [TAGW-1:0] tag_in,
input wire [`INST_FRM_BITS-1:0] frm,
input wire do_madd,
input wire do_sub,
input wire do_neg,
input wire [NUM_LANES-1:0][31:0] dataa,
input wire [NUM_LANES-1:0][31:0] datab,
input wire [NUM_LANES-1:0][31:0] datac,
output wire [NUM_LANES-1:0][31:0] result,
output wire has_fflags,
output fflags_t [NUM_LANES-1:0] fflags,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
);
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
for (genvar i = 0; i < NUM_LANES; ++i) begin
reg [31:0] a, b, c;
always @(*) begin
if (do_madd) begin
// MADD/MSUB/NMADD/NMSUB
a = do_neg ? {~dataa[i][31], dataa[i][30:0]} : dataa[i];
b = datab[i];
c = (do_neg ^ do_sub) ? {~datac[i][31], datac[i][30:0]} : datac[i];
end else begin
if (do_neg) begin
// MUL
a = dataa[i];
b = datab[i];
c = 0;
end else begin
// ADD/SUB
a = 32'h3f800000; // 1.0f
b = dataa[i];
c = do_sub ? {~datab[i][31], datab[i][30:0]} : datab[i];
end
end
end
acl_fmadd fmadd (
.clk (clk),
.areset (1'b0),
.en (enable),
.a (a),
.b (b),
.c (c),
.q (result[i])
);
end
VX_shift_register #(
.DATAW (1 + TAGW),
.DEPTH (LATENCY),
.RESETW (1)
) shift_reg (
.clk(clk),
.reset (reset),
.enable (enable),
.data_in ({valid_in, tag_in}),
.data_out ({valid_out, tag_out})
);
assign ready_in = enable;
`UNUSED_VAR (frm)
assign has_fflags = 0;
assign fflags = 0;
endmodule

60
hw/ip/altera/stratix10/VX_acl_fsqrt.sv
View file

@ -1,60 +0,0 @@
`include "VX_fpu_define.vh"
module VX_acl_fsqrt #(
parameter NUM_LANES = 1,
parameter TAGW = 1,
parameter LATENCY = 25
) (
input wire clk,
input wire reset,
output wire ready_in,
input wire valid_in,
input wire [TAGW-1:0] tag_in,
input wire [`INST_FRM_BITS-1:0] frm,
input wire [NUM_LANES-1:0][31:0] dataa,
output wire [NUM_LANES-1:0][31:0] result,
output wire has_fflags,
output fflags_t [NUM_LANES-1:0] fflags,
output wire [TAGW-1:0] tag_out,
input wire ready_out,
output wire valid_out
);
wire stall = ~ready_out && valid_out;
wire enable = ~stall;
for (genvar i = 0; i < NUM_LANES; ++i) begin
acl_fsqrt fsqrt (
.clk (clk),
.areset (1'b0),
.en (enable),
.a (dataa[i]),
.q (result[i])
);
end
VX_shift_register #(
.DATAW (1 + TAGW),
.DEPTH (LATENCY),
.RESETW (1)
) shift_reg (
.clk (clk),
.reset (reset),
.enable (enable),
.data_in ({valid_in, tag_in}),
.data_out ({valid_out, tag_out})
);
assign ready_in = enable;
`UNUSED_VAR (frm)
assign has_fflags = 0;
assign fflags = 0;
endmodule

25
hw/ip/xilinx/alveo/VX_xil_fdiv.sv → hw/ip/xilinx/VX_xil_fdiv.sv
View file

@ -32,22 +32,17 @@ module VX_xil_fdiv #(
for (genvar i = 0; i < NUM_LANES; ++i) begin
wire [3:0] tuser;
wire tvalid_in;
`RESET_RELAY (fdiv_reset, reset);
assign tvalid_in = enable && valid_in;
xil_fdiv fdiv (
.aclk (clk),
.aresetn (~fdiv_reset),
.s_axis_a_tvalid (tvalid_in),
.s_axis_a_tdata (a),
.s_axis_b_tvalid (tvalid_in),
.s_axis_b_tdata (b),
.m_axis_result_tvalid (valid_out),
.aclken (enable),
.s_axis_a_tvalid (1'b1),
.s_axis_a_tdata (dataa[i]),
.s_axis_b_tvalid (1'b1),
.s_axis_b_tdata (datab[i]),
`UNUSED_PIN (m_axis_result_tvalid),
.m_axis_result_tdata (result[i]),
.m_axis_result_tuser (tuser[i])
.m_axis_result_tuser (tuser)
);
assign fflags[i].NX = 1'b0;
@ -58,15 +53,15 @@ module VX_xil_fdiv #(
end
VX_shift_register #(
.DATAW (TAGW),
.DATAW (1 + TAGW),
.DEPTH (LATENCY),
.RESETW (1)
) shift_reg (
.clk (clk),
.reset (reset),
.enable (enable),
.data_in (tag_in),
.data_out (tag_out)
.data_in ({valid_in, tag_in}),
.data_out ({valid_out, tag_out})
);
assign ready_in = enable;

19
hw/ip/xilinx/alveo/VX_xil_fma.sv → hw/ip/xilinx/VX_xil_fma.sv
View file

@ -38,7 +38,6 @@ module VX_xil_fma #(
for (genvar i = 0; i < NUM_LANES; ++i) begin
reg [31:0] a, b, c;
wire [2:0] tuser;
wire tvalid_in;
always @(*) begin
if (do_madd) begin
@ -60,25 +59,19 @@ module VX_xil_fma #(
end
end
end
`RESET_RELAY (fma_reset, reset);
assign tvalid_in = enable && valid_in;
xil_fma fma (
.aclk (clk),
.aresetn (~fma_reset),
.s_axis_a_tvalid (tvalid_in),
.aclken (enable),
.s_axis_a_tvalid (1'b1),
.s_axis_a_tdata (a),
.s_axis_b_tvalid (tvalid_in),
.s_axis_b_tvalid (1'b1),
.s_axis_b_tdata (b),
.s_axis_c_tvalid (tvalid_in),
.s_axis_c_tvalid (1'b1),
.s_axis_c_tdata (c),
.s_axis_operation_tvalid (tvalid_in),
.s_axis_operation_tdata ('0),
.m_axis_result_tvalid (valid_out),
`UNUSED_PIN (m_axis_result_tvalid),
.m_axis_result_tdata (result[i]),
.m_axis_result_tuser (tuser[i])
.m_axis_result_tuser (tuser)
);
assign fflags[i].NX = 1'b0;

17
hw/ip/xilinx/alveo/VX_xil_fsqrt.sv → hw/ip/xilinx/VX_xil_fsqrt.sv
View file

@ -30,21 +30,16 @@ module VX_xil_fsqrt #(
wire enable = ~stall;
for (genvar i = 0; i < NUM_LANES; ++i) begin
wire [0:0] tuser;
wire tvalid_in;
`RESET_RELAY (fsqrt_reset, reset);
assign tvalid_in = enable && valid_in;
wire [0:0] tuser;
xil_fsqrt fsqrt (
.aclk (clk),
.aresetn (~fsqrt_reset),
.s_axis_a_tvalid (tvalid_in),
.s_axis_a_tdata (a),
.m_axis_result_tvalid (valid_out),
.aclken (enable),
.s_axis_a_tvalid (1'b1),
.s_axis_a_tdata (dataa[i]),
`UNUSED_PIN (m_axis_result_tvalid),
.m_axis_result_tdata (result[i]),
.m_axis_result_tuser (tuser[i])
.m_axis_result_tuser (tuser)
);
assign fflags[i].NX = 1'b0;

200
hw/ip/xilinx/alveo/xil_fdiv.v
View file

@ -1,200 +0,0 @@
// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:floating_point:7.1
// IP Revision: 11
(* X_CORE_INFO = "floating_point_v7_1_11,Vivado 2020.2.2" *)
(* CHECK_LICENSE_TYPE = "fdiv,floating_point_v7_1_11,{}" *)
(* CORE_GENERATION_INFO = "fdiv,floating_point_v7_1_11,{x_ipProduct=Vivado 2020.2.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=11,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_XDEVICEFAMILY=virtexuplusHBM,C_PART=xcu280-fsvh2892-2L-e,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_F\
MA=0,C_HAS_FMS=0,C_HAS_UNFUSED_MULTIPLY_ADD=0,C_HAS_UNFUSED_MULTIPLY_SUB=0,C_HAS_UNFUSED_MULTIPLY_ACCUMULATOR_A=0,C_HAS_UNFUSED_MULTIPLY_ACCUMULATOR_S=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_HAS_ACCUMULATOR_PRIMITIVE_A=0,C_HAS_ACCUMULATOR_PRIMITIVE_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=28,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=\
1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=1,C_HAS_OVERFLOW=1,C_HAS_INVALID_OP=1,C_HAS_DIVIDE_BY_ZERO=1,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=1,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_\
A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=4,C_FIXED_DATA_UNSIGNED=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module xil_fdiv (
aclk,
s_axis_a_tvalid,
s_axis_a_tdata,
s_axis_b_tvalid,
s_axis_b_tdata,
m_axis_result_tvalid,
m_axis_result_tdata,
m_axis_result_tuser
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_OPERATION:M_AXIS_RESULT:S_AXIS_C:S_AXIS_B:S_AXIS_A, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID" *)
input wire s_axis_a_tvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA" *)
input wire [31 : 0] s_axis_a_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID" *)
input wire s_axis_b_tvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA" *)
input wire [31 : 0] s_axis_b_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID" *)
output wire m_axis_result_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA" *)
output wire [31 : 0] m_axis_result_tdata;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_RESULT, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TUSER" *)
output wire [3 : 0] m_axis_result_tuser;
floating_point_v7_1_11 #(
.C_XDEVICEFAMILY("virtexuplusHBM"),
.C_PART("xcu280-fsvh2892-2L-e"),
.C_HAS_ADD(0),
.C_HAS_SUBTRACT(0),
.C_HAS_MULTIPLY(0),
.C_HAS_DIVIDE(1),
.C_HAS_SQRT(0),
.C_HAS_COMPARE(0),
.C_HAS_FIX_TO_FLT(0),
.C_HAS_FLT_TO_FIX(0),
.C_HAS_FLT_TO_FLT(0),
.C_HAS_RECIP(0),
.C_HAS_RECIP_SQRT(0),
.C_HAS_ABSOLUTE(0),
.C_HAS_LOGARITHM(0),
.C_HAS_EXPONENTIAL(0),
.C_HAS_FMA(0),
.C_HAS_FMS(0),
.C_HAS_UNFUSED_MULTIPLY_ADD(0),
.C_HAS_UNFUSED_MULTIPLY_SUB(0),
.C_HAS_UNFUSED_MULTIPLY_ACCUMULATOR_A(0),
.C_HAS_UNFUSED_MULTIPLY_ACCUMULATOR_S(0),
.C_HAS_ACCUMULATOR_A(0),
.C_HAS_ACCUMULATOR_S(0),
.C_HAS_ACCUMULATOR_PRIMITIVE_A(0),
.C_HAS_ACCUMULATOR_PRIMITIVE_S(0),
.C_A_WIDTH(32),
.C_A_FRACTION_WIDTH(24),
.C_B_WIDTH(32),
.C_B_FRACTION_WIDTH(24),
.C_C_WIDTH(32),
.C_C_FRACTION_WIDTH(24),
.C_RESULT_WIDTH(32),
.C_RESULT_FRACTION_WIDTH(24),
.C_COMPARE_OPERATION(8),
.C_LATENCY(28),
.C_OPTIMIZATION(1),
.C_MULT_USAGE(0),
.C_BRAM_USAGE(0),
.C_RATE(1),
.C_ACCUM_INPUT_MSB(32),
.C_ACCUM_MSB(32),
.C_ACCUM_LSB(-31),
.C_HAS_UNDERFLOW(1),
.C_HAS_OVERFLOW(1),
.C_HAS_INVALID_OP(1),
.C_HAS_DIVIDE_BY_ZERO(1),
.C_HAS_ACCUM_OVERFLOW(0),
.C_HAS_ACCUM_INPUT_OVERFLOW(0),
.C_HAS_ACLKEN(0),
.C_HAS_ARESETN(0),
.C_THROTTLE_SCHEME(3),
.C_HAS_A_TUSER(0),
.C_HAS_A_TLAST(0),
.C_HAS_B(1),
.C_HAS_B_TUSER(0),
.C_HAS_B_TLAST(0),
.C_HAS_C(0),
.C_HAS_C_TUSER(0),
.C_HAS_C_TLAST(0),
.C_HAS_OPERATION(0),
.C_HAS_OPERATION_TUSER(0),
.C_HAS_OPERATION_TLAST(0),
.C_HAS_RESULT_TUSER(1),
.C_HAS_RESULT_TLAST(0),
.C_TLAST_RESOLUTION(0),
.C_A_TDATA_WIDTH(32),
.C_A_TUSER_WIDTH(1),
.C_B_TDATA_WIDTH(32),
.C_B_TUSER_WIDTH(1),
.C_C_TDATA_WIDTH(32),
.C_C_TUSER_WIDTH(1),
.C_OPERATION_TDATA_WIDTH(8),
.C_OPERATION_TUSER_WIDTH(1),
.C_RESULT_TDATA_WIDTH(32),
.C_RESULT_TUSER_WIDTH(4),
.C_FIXED_DATA_UNSIGNED(0)
) inst (
.aclk(aclk),
.aclken(1'H1),
.aresetn(1'H1),
.s_axis_a_tvalid(s_axis_a_tvalid),
.s_axis_a_tready(),
.s_axis_a_tdata(s_axis_a_tdata),
.s_axis_a_tuser(1'B0),
.s_axis_a_tlast(1'H0),
.s_axis_b_tvalid(s_axis_b_tvalid),
.s_axis_b_tready(),
.s_axis_b_tdata(s_axis_b_tdata),
.s_axis_b_tuser(1'B0),
.s_axis_b_tlast(1'H0),
.s_axis_c_tvalid(1'H0),
.s_axis_c_tready(),
.s_axis_c_tdata(32'B0),
.s_axis_c_tuser(1'B0),
.s_axis_c_tlast(1'H0),
.s_axis_operation_tvalid(1'H0),
.s_axis_operation_tready(),
.s_axis_operation_tdata(8'B0),
.s_axis_operation_tuser(1'B0),
.s_axis_operation_tlast(1'H0),
.m_axis_result_tvalid(m_axis_result_tvalid),
.m_axis_result_tready(1'H0),
.m_axis_result_tdata(m_axis_result_tdata),
.m_axis_result_tuser(m_axis_result_tuser),
.m_axis_result_tlast()
);
endmodule

214
hw/ip/xilinx/alveo/xil_fma.v
View file

@ -1,214 +0,0 @@
// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:floating_point:7.1
// IP Revision: 11
(* X_CORE_INFO = "floating_point_v7_1_11,Vivado 2020.2.2" *)
(* CHECK_LICENSE_TYPE = "fmadd,floating_point_v7_1_11,{}" *)
(* CORE_GENERATION_INFO = "fmadd,floating_point_v7_1_11,{x_ipProduct=Vivado 2020.2.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=11,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_XDEVICEFAMILY=virtexuplusHBM,C_PART=xcu280-fsvh2892-2L-e,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_\
FMA=1,C_HAS_FMS=1,C_HAS_UNFUSED_MULTIPLY_ADD=0,C_HAS_UNFUSED_MULTIPLY_SUB=0,C_HAS_UNFUSED_MULTIPLY_ACCUMULATOR_A=0,C_HAS_UNFUSED_MULTIPLY_ACCUMULATOR_S=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_HAS_ACCUMULATOR_PRIMITIVE_A=0,C_HAS_ACCUMULATOR_PRIMITIVE_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=16,C_OPTIMIZATION=1,C_MULT_USAGE=1,C_BRAM_USAGE=0,C_RATE\
=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=1,C_HAS_OVERFLOW=1,C_HAS_INVALID_OP=1,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=1,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=1,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=1,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C\
_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=3,C_FIXED_DATA_UNSIGNED=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module xil_fma (
aclk,
s_axis_a_tvalid,
s_axis_a_tdata,
s_axis_b_tvalid,
s_axis_b_tdata,
s_axis_c_tvalid,
s_axis_c_tdata,
s_axis_operation_tvalid,
s_axis_operation_tdata,
m_axis_result_tvalid,
m_axis_result_tdata,
m_axis_result_tuser
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_OPERATION:M_AXIS_RESULT:S_AXIS_C:S_AXIS_B:S_AXIS_A, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID" *)
input wire s_axis_a_tvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA" *)
input wire [31 : 0] s_axis_a_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID" *)
input wire s_axis_b_tvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA" *)
input wire [31 : 0] s_axis_b_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_C TVALID" *)
input wire s_axis_c_tvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_C, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_C TDATA" *)
input wire [31 : 0] s_axis_c_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TVALID" *)
input wire s_axis_operation_tvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_OPERATION, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TDATA" *)
input wire [7 : 0] s_axis_operation_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID" *)
output wire m_axis_result_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA" *)
output wire [31 : 0] m_axis_result_tdata;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_RESULT, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 3, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TUSER" *)
output wire [2 : 0] m_axis_result_tuser;
floating_point_v7_1_11 #(
.C_XDEVICEFAMILY("virtexuplusHBM"),
.C_PART("xcu280-fsvh2892-2L-e"),
.C_HAS_ADD(0),
.C_HAS_SUBTRACT(0),
.C_HAS_MULTIPLY(0),
.C_HAS_DIVIDE(0),
.C_HAS_SQRT(0),
.C_HAS_COMPARE(0),
.C_HAS_FIX_TO_FLT(0),
.C_HAS_FLT_TO_FIX(0),
.C_HAS_FLT_TO_FLT(0),
.C_HAS_RECIP(0),
.C_HAS_RECIP_SQRT(0),
.C_HAS_ABSOLUTE(0),
.C_HAS_LOGARITHM(0),
.C_HAS_EXPONENTIAL(0),
.C_HAS_FMA(1),
.C_HAS_FMS(1),
.C_HAS_UNFUSED_MULTIPLY_ADD(0),
.C_HAS_UNFUSED_MULTIPLY_SUB(0),
.C_HAS_UNFUSED_MULTIPLY_ACCUMULATOR_A(0),
.C_HAS_UNFUSED_MULTIPLY_ACCUMULATOR_S(0),
.C_HAS_ACCUMULATOR_A(0),
.C_HAS_ACCUMULATOR_S(0),
.C_HAS_ACCUMULATOR_PRIMITIVE_A(0),
.C_HAS_ACCUMULATOR_PRIMITIVE_S(0),
.C_A_WIDTH(32),
.C_A_FRACTION_WIDTH(24),
.C_B_WIDTH(32),
.C_B_FRACTION_WIDTH(24),
.C_C_WIDTH(32),
.C_C_FRACTION_WIDTH(24),
.C_RESULT_WIDTH(32),
.C_RESULT_FRACTION_WIDTH(24),
.C_COMPARE_OPERATION(8),
.C_LATENCY(16),
.C_OPTIMIZATION(1),
.C_MULT_USAGE(1),
.C_BRAM_USAGE(0),
.C_RATE(1),
.C_ACCUM_INPUT_MSB(32),
.C_ACCUM_MSB(32),
.C_ACCUM_LSB(-31),
.C_HAS_UNDERFLOW(1),
.C_HAS_OVERFLOW(1),
.C_HAS_INVALID_OP(1),
.C_HAS_DIVIDE_BY_ZERO(0),
.C_HAS_ACCUM_OVERFLOW(0),
.C_HAS_ACCUM_INPUT_OVERFLOW(0),
.C_HAS_ACLKEN(0),
.C_HAS_ARESETN(0),
.C_THROTTLE_SCHEME(3),
.C_HAS_A_TUSER(0),
.C_HAS_A_TLAST(0),
.C_HAS_B(1),
.C_HAS_B_TUSER(0),
.C_HAS_B_TLAST(0),
.C_HAS_C(1),
.C_HAS_C_TUSER(0),
.C_HAS_C_TLAST(0),
.C_HAS_OPERATION(1),
.C_HAS_OPERATION_TUSER(0),
.C_HAS_OPERATION_TLAST(0),
.C_HAS_RESULT_TUSER(1),
.C_HAS_RESULT_TLAST(0),
.C_TLAST_RESOLUTION(0),
.C_A_TDATA_WIDTH(32),
.C_A_TUSER_WIDTH(1),
.C_B_TDATA_WIDTH(32),
.C_B_TUSER_WIDTH(1),
.C_C_TDATA_WIDTH(32),
.C_C_TUSER_WIDTH(1),
.C_OPERATION_TDATA_WIDTH(8),
.C_OPERATION_TUSER_WIDTH(1),
.C_RESULT_TDATA_WIDTH(32),
.C_RESULT_TUSER_WIDTH(3),
.C_FIXED_DATA_UNSIGNED(0)
) inst (
.aclk(aclk),
.aclken(1'H1),
.aresetn(1'H1),
.s_axis_a_tvalid(s_axis_a_tvalid),
.s_axis_a_tready(),
.s_axis_a_tdata(s_axis_a_tdata),
.s_axis_a_tuser(1'B0),
.s_axis_a_tlast(1'H0),
.s_axis_b_tvalid(s_axis_b_tvalid),
.s_axis_b_tready(),
.s_axis_b_tdata(s_axis_b_tdata),
.s_axis_b_tuser(1'B0),
.s_axis_b_tlast(1'H0),
.s_axis_c_tvalid(s_axis_c_tvalid),
.s_axis_c_tready(),
.s_axis_c_tdata(s_axis_c_tdata),
.s_axis_c_tuser(1'B0),
.s_axis_c_tlast(1'H0),
.s_axis_operation_tvalid(s_axis_operation_tvalid),
.s_axis_operation_tready(),
.s_axis_operation_tdata(s_axis_operation_tdata),
.s_axis_operation_tuser(1'B0),
.s_axis_operation_tlast(1'H0),
.m_axis_result_tvalid(m_axis_result_tvalid),
.m_axis_result_tready(1'H0),
.m_axis_result_tdata(m_axis_result_tdata),
.m_axis_result_tuser(m_axis_result_tuser),
.m_axis_result_tlast()
);
endmodule

193
hw/ip/xilinx/alveo/xil_fsqrt.v
View file

@ -1,193 +0,0 @@
// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:floating_point:7.1
// IP Revision: 11
(* X_CORE_INFO = "floating_point_v7_1_11,Vivado 2020.2.2" *)
(* CHECK_LICENSE_TYPE = "fsqrt,floating_point_v7_1_11,{}" *)
(* CORE_GENERATION_INFO = "fsqrt,floating_point_v7_1_11,{x_ipProduct=Vivado 2020.2.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=11,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_XDEVICEFAMILY=virtexuplusHBM,C_PART=xcu280-fsvh2892-2L-e,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=1,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_\
FMA=0,C_HAS_FMS=0,C_HAS_UNFUSED_MULTIPLY_ADD=0,C_HAS_UNFUSED_MULTIPLY_SUB=0,C_HAS_UNFUSED_MULTIPLY_ACCUMULATOR_A=0,C_HAS_UNFUSED_MULTIPLY_ACCUMULATOR_S=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_HAS_ACCUMULATOR_PRIMITIVE_A=0,C_HAS_ACCUMULATOR_PRIMITIVE_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=28,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE\
=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=1,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=1,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C\
_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module xil_fsqrt (
aclk,
s_axis_a_tvalid,
s_axis_a_tdata,
m_axis_result_tvalid,
m_axis_result_tdata,
m_axis_result_tuser
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_OPERATION:M_AXIS_RESULT:S_AXIS_C:S_AXIS_B:S_AXIS_A, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID" *)
input wire s_axis_a_tvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA" *)
input wire [31 : 0] s_axis_a_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID" *)
output wire m_axis_result_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA" *)
output wire [31 : 0] m_axis_result_tdata;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_RESULT, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TUSER" *)
output wire [0 : 0] m_axis_result_tuser;
floating_point_v7_1_11 #(
.C_XDEVICEFAMILY("virtexuplusHBM"),
.C_PART("xcu280-fsvh2892-2L-e"),
.C_HAS_ADD(0),
.C_HAS_SUBTRACT(0),
.C_HAS_MULTIPLY(0),
.C_HAS_DIVIDE(0),
.C_HAS_SQRT(1),
.C_HAS_COMPARE(0),
.C_HAS_FIX_TO_FLT(0),
.C_HAS_FLT_TO_FIX(0),
.C_HAS_FLT_TO_FLT(0),
.C_HAS_RECIP(0),
.C_HAS_RECIP_SQRT(0),
.C_HAS_ABSOLUTE(0),
.C_HAS_LOGARITHM(0),
.C_HAS_EXPONENTIAL(0),
.C_HAS_FMA(0),
.C_HAS_FMS(0),
.C_HAS_UNFUSED_MULTIPLY_ADD(0),
.C_HAS_UNFUSED_MULTIPLY_SUB(0),
.C_HAS_UNFUSED_MULTIPLY_ACCUMULATOR_A(0),
.C_HAS_UNFUSED_MULTIPLY_ACCUMULATOR_S(0),
.C_HAS_ACCUMULATOR_A(0),
.C_HAS_ACCUMULATOR_S(0),
.C_HAS_ACCUMULATOR_PRIMITIVE_A(0),
.C_HAS_ACCUMULATOR_PRIMITIVE_S(0),
.C_A_WIDTH(32),
.C_A_FRACTION_WIDTH(24),
.C_B_WIDTH(32),
.C_B_FRACTION_WIDTH(24),
.C_C_WIDTH(32),
.C_C_FRACTION_WIDTH(24),
.C_RESULT_WIDTH(32),
.C_RESULT_FRACTION_WIDTH(24),
.C_COMPARE_OPERATION(8),
.C_LATENCY(28),
.C_OPTIMIZATION(1),
.C_MULT_USAGE(0),
.C_BRAM_USAGE(0),
.C_RATE(1),
.C_ACCUM_INPUT_MSB(32),
.C_ACCUM_MSB(32),
.C_ACCUM_LSB(-31),
.C_HAS_UNDERFLOW(0),
.C_HAS_OVERFLOW(0),
.C_HAS_INVALID_OP(1),
.C_HAS_DIVIDE_BY_ZERO(0),
.C_HAS_ACCUM_OVERFLOW(0),
.C_HAS_ACCUM_INPUT_OVERFLOW(0),
.C_HAS_ACLKEN(0),
.C_HAS_ARESETN(0),
.C_THROTTLE_SCHEME(3),
.C_HAS_A_TUSER(0),
.C_HAS_A_TLAST(0),
.C_HAS_B(0),
.C_HAS_B_TUSER(0),
.C_HAS_B_TLAST(0),
.C_HAS_C(0),
.C_HAS_C_TUSER(0),
.C_HAS_C_TLAST(0),
.C_HAS_OPERATION(0),
.C_HAS_OPERATION_TUSER(0),
.C_HAS_OPERATION_TLAST(0),
.C_HAS_RESULT_TUSER(1),
.C_HAS_RESULT_TLAST(0),
.C_TLAST_RESOLUTION(0),
.C_A_TDATA_WIDTH(32),
.C_A_TUSER_WIDTH(1),
.C_B_TDATA_WIDTH(32),
.C_B_TUSER_WIDTH(1),
.C_C_TDATA_WIDTH(32),
.C_C_TUSER_WIDTH(1),
.C_OPERATION_TDATA_WIDTH(8),
.C_OPERATION_TUSER_WIDTH(1),
.C_RESULT_TDATA_WIDTH(32),
.C_RESULT_TUSER_WIDTH(1),
.C_FIXED_DATA_UNSIGNED(0)
) inst (
.aclk(aclk),
.aclken(1'H1),
.aresetn(1'H1),
.s_axis_a_tvalid(s_axis_a_tvalid),
.s_axis_a_tready(),
.s_axis_a_tdata(s_axis_a_tdata),
.s_axis_a_tuser(1'B0),
.s_axis_a_tlast(1'H0),
.s_axis_b_tvalid(1'H0),
.s_axis_b_tready(),
.s_axis_b_tdata(32'B0),
.s_axis_b_tuser(1'B0),
.s_axis_b_tlast(1'H0),
.s_axis_c_tvalid(1'H0),
.s_axis_c_tready(),
.s_axis_c_tdata(32'B0),
.s_axis_c_tuser(1'B0),
.s_axis_c_tlast(1'H0),
.s_axis_operation_tvalid(1'H0),
.s_axis_operation_tready(),
.s_axis_operation_tdata(8'B0),
.s_axis_operation_tuser(1'B0),
.s_axis_operation_tlast(1'H0),
.m_axis_result_tvalid(m_axis_result_tvalid),
.m_axis_result_tready(1'H0),
.m_axis_result_tdata(m_axis_result_tdata),
.m_axis_result_tuser(m_axis_result_tuser),
.m_axis_result_tlast()
);
endmodule

6
hw/rtl/VX_config.vh
View file

@ -68,11 +68,11 @@
`define MEM_BLOCK_SIZE 64
`endif
`ifndef L1_BLOCK_SIZE
`ifndef L1_LINE_SIZE
`ifdef L1_DISABLE
`define L1_BLOCK_SIZE ((`L2_ENABLED || `L3_ENABLED) ? 4 : `MEM_BLOCK_SIZE)
`define L1_LINE_SIZE ((`L2_ENABLED || `L3_ENABLED) ? 4 : `MEM_BLOCK_SIZE)
`else
`define L1_BLOCK_SIZE ((`L2_ENABLED || `L3_ENABLED) ? 16 : `MEM_BLOCK_SIZE)
`define L1_LINE_SIZE ((`L2_ENABLED || `L3_ENABLED) ? 16 : `MEM_BLOCK_SIZE)
`endif
`endif

18
hw/rtl/VX_define.vh
View file

@ -272,9 +272,21 @@
///////////////////////////////////////////////////////////////////////////////
`define VX_MEM_BYTEEN_WIDTH L3_LINE_SIZE
`define VX_MEM_ADDR_WIDTH (32 - `CLOG2(L3_LINE_SIZE))
`define VX_MEM_DATA_WIDTH L3_MEM_DATA_WIDTH
`ifdef L2_ENABLE
`define L2_LINE_SIZE `MEM_BLOCK_SIZE
`else
`define L2_LINE_SIZE `L1_LINE_SIZE
`endif
`ifdef L3_ENABLE
`define L3_LINE_SIZE `MEM_BLOCK_SIZE
`else
`define L3_LINE_SIZE `L2_LINE_SIZE
`endif
`define VX_MEM_BYTEEN_WIDTH `L3_LINE_SIZE
`define VX_MEM_ADDR_WIDTH (32 - `CLOG2(`L3_LINE_SIZE))
`define VX_MEM_DATA_WIDTH (`L3_LINE_SIZE * 8)
`define VX_MEM_TAG_WIDTH L3_MEM_TAG_WIDTH
`define VX_DCR_ADDR_WIDTH `DCR_ADDR_BITS
`define VX_DCR_DATA_WIDTH 32

40
hw/rtl/VX_gpu_types.vh
View file

@ -42,7 +42,7 @@ localparam ICACHE_WORD_SIZE = 4;
localparam ICACHE_ADDR_WIDTH = (32 - `CLOG2(ICACHE_WORD_SIZE));
// Block size in bytes
localparam ICACHE_LINE_SIZE = `L1_BLOCK_SIZE;
localparam ICACHE_LINE_SIZE = `L1_LINE_SIZE;
// Core request tag Id bits
localparam ICACHE_TAG_ID_BITS = `UP(`NW_BITS);
@ -74,7 +74,7 @@ localparam DCACHE_WORD_SIZE = 4;
localparam DCACHE_ADDR_WIDTH = (32 - `CLOG2(DCACHE_WORD_SIZE));
// Block size in bytes
localparam DCACHE_LINE_SIZE = `L1_BLOCK_SIZE;
localparam DCACHE_LINE_SIZE = `L1_LINE_SIZE;
// Input request size
localparam DCACHE_NUM_REQS = `MAX(`DCACHE_NUM_BANKS, `SMEM_NUM_BANKS);
@ -112,7 +112,7 @@ localparam TCACHE_WORD_SIZE = 4;
localparam TCACHE_ADDR_WIDTH = (32 - `CLOG2(TCACHE_WORD_SIZE));
// Block size in bytes
localparam TCACHE_LINE_SIZE = `L1_BLOCK_SIZE;
localparam TCACHE_LINE_SIZE = `L1_LINE_SIZE;
// Input request size
localparam TCACHE_NUM_REQS = `TCACHE_NUM_BANKS;
@ -146,7 +146,7 @@ localparam RCACHE_WORD_SIZE = 4;
localparam RCACHE_ADDR_WIDTH = (32 - `CLOG2(RCACHE_WORD_SIZE));
// Block size in bytes
localparam RCACHE_LINE_SIZE = `L1_BLOCK_SIZE;
localparam RCACHE_LINE_SIZE = `L1_LINE_SIZE;
// Input request size
localparam RCACHE_NUM_REQS = `RCACHE_NUM_BANKS;
@ -180,7 +180,7 @@ localparam OCACHE_WORD_SIZE = 4;
localparam OCACHE_ADDR_WIDTH = (32 - `CLOG2(OCACHE_WORD_SIZE));
// Block size in bytes
localparam OCACHE_LINE_SIZE = `L1_BLOCK_SIZE;
localparam OCACHE_LINE_SIZE = `L1_LINE_SIZE;
// Input request size
localparam OCACHE_NUM_REQS = `OCACHE_NUM_BANKS;
@ -219,14 +219,7 @@ localparam NUM_L1_OUTPUTS = (2 + `EXT_TEX_ENABLED + `EXT_RASTER_ENABLED +
/////////////////////////////// L2 Parameters /////////////////////////////////
// Word size in bytes
localparam L2_WORD_SIZE = `L1_BLOCK_SIZE;
// Block size in bytes
`ifdef L2_ENABLE
localparam L2_LINE_SIZE = `MEM_BLOCK_SIZE;
`else
localparam L2_LINE_SIZE = L2_WORD_SIZE;
`endif
localparam L2_WORD_SIZE = `L1_LINE_SIZE;
// Input request size
localparam L2_NUM_REQS = NUM_L1_OUTPUTS;
@ -235,26 +228,19 @@ localparam L2_NUM_REQS = NUM_L1_OUTPUTS;
localparam L2_TAG_WIDTH = L1_MEM_TAG_WIDTH;
// Memory request data bits
localparam L2_MEM_DATA_WIDTH = (L2_LINE_SIZE * 8);
localparam L2_MEM_DATA_WIDTH = (`L2_LINE_SIZE * 8);
// Memory request tag bits
`ifdef L2_ENABLE
localparam L2_MEM_TAG_WIDTH = `CACHE_NC_MEM_TAG_WIDTH(`L2_MSHR_SIZE, `L2_NUM_BANKS, L2_NUM_REQS, L2_LINE_SIZE, L2_WORD_SIZE, L2_TAG_WIDTH);
localparam L2_MEM_TAG_WIDTH = `CACHE_NC_MEM_TAG_WIDTH(`L2_MSHR_SIZE, `L2_NUM_BANKS, L2_NUM_REQS, `L2_LINE_SIZE, L2_WORD_SIZE, L2_TAG_WIDTH);
`else
localparam L2_MEM_TAG_WIDTH = `CACHE_NC_BYPASS_TAG_WIDTH(L2_NUM_REQS, L2_LINE_SIZE, L2_WORD_SIZE, L2_TAG_WIDTH);
localparam L2_MEM_TAG_WIDTH = `CACHE_NC_BYPASS_TAG_WIDTH(L2_NUM_REQS, `L2_LINE_SIZE, L2_WORD_SIZE, L2_TAG_WIDTH);
`endif
/////////////////////////////// L3 Parameters /////////////////////////////////
// Word size in bytes
localparam L3_WORD_SIZE = L2_LINE_SIZE;
// Block size in bytes
`ifdef L3_ENABLE
localparam L3_LINE_SIZE = `MEM_BLOCK_SIZE;
`else
localparam L3_LINE_SIZE = L3_WORD_SIZE;
`endif
localparam L3_WORD_SIZE = `L2_LINE_SIZE;
// Input request size
localparam L3_NUM_REQS = `NUM_CLUSTERS;
@ -263,13 +249,13 @@ localparam L3_NUM_REQS = `NUM_CLUSTERS;
localparam L3_TAG_WIDTH = L2_MEM_TAG_WIDTH;
// Memory request data bits
localparam L3_MEM_DATA_WIDTH = (L3_LINE_SIZE * 8);
localparam L3_MEM_DATA_WIDTH = (`L3_LINE_SIZE * 8);
// Memory request tag bits
`ifdef L3_ENABLE
localparam L3_MEM_TAG_WIDTH = `CACHE_NC_MEM_TAG_WIDTH(`L3_MSHR_SIZE, `L3_NUM_BANKS, L3_NUM_REQS, L3_LINE_SIZE, L3_WORD_SIZE, L3_TAG_WIDTH);
localparam L3_MEM_TAG_WIDTH = `CACHE_NC_MEM_TAG_WIDTH(`L3_MSHR_SIZE, `L3_NUM_BANKS, L3_NUM_REQS, `L3_LINE_SIZE, L3_WORD_SIZE, L3_TAG_WIDTH);
`else
localparam L3_MEM_TAG_WIDTH = `CACHE_NC_BYPASS_TAG_WIDTH(L3_NUM_REQS, L3_LINE_SIZE, L3_WORD_SIZE, L3_TAG_WIDTH);
localparam L3_MEM_TAG_WIDTH = `CACHE_NC_BYPASS_TAG_WIDTH(L3_NUM_REQS, `L3_LINE_SIZE, L3_WORD_SIZE, L3_TAG_WIDTH);
`endif
endpackage

2
hw/rtl/VX_mem_unit.sv
View file

@ -497,7 +497,7 @@ module VX_mem_unit # (
VX_cache_wrap #(
.INSTANCE_ID ($sformatf("cluster%0d-l2cache", CLUSTER_ID)),
.CACHE_SIZE (`L2_CACHE_SIZE),
.LINE_SIZE (L2_LINE_SIZE),
.LINE_SIZE (`L2_LINE_SIZE),
.NUM_BANKS (`L2_NUM_BANKS),
.NUM_WAYS (`L2_NUM_WAYS),
.NUM_PORTS (`L2_NUM_PORTS),

4
hw/rtl/VX_platform.vh
View file

@ -1,6 +1,10 @@
`ifndef VX_PLATFORM_VH
`define VX_PLATFORM_VH
`ifndef SIMULATION
`include "globals.vh"
`endif
`ifndef SYNTHESIS
`include "util_dpi.vh"
`endif

2
hw/rtl/Vortex.sv
View file

@ -202,7 +202,7 @@ module Vortex (
VX_cache_wrap #(
.INSTANCE_ID ("l3cache"),
.CACHE_SIZE (`L3_CACHE_SIZE),
.LINE_SIZE (L3_LINE_SIZE),
.LINE_SIZE (`L3_LINE_SIZE),
.NUM_BANKS (`L3_NUM_BANKS),
.NUM_WAYS (`L3_NUM_WAYS),
.NUM_PORTS (`L3_NUM_PORTS),

28
hw/rtl/Vortex_axi.sv
View file

@ -6,10 +6,9 @@ import VX_gpu_types::*;
`IGNORE_WARNINGS_END
module Vortex_axi #(
parameter AXI_DATA_WIDTH = `VX_MEM_DATA_WIDTH,
parameter AXI_ADDR_WIDTH = 32,
parameter AXI_TID_WIDTH = `VX_MEM_TAG_WIDTH,
parameter AXI_STROBE_WIDTH = (AXI_DATA_WIDTH / 8)
parameter AXI_DATA_WIDTH = `VX_MEM_DATA_WIDTH,
parameter AXI_ADDR_WIDTH = 32,
parameter AXI_TID_WIDTH = `VX_MEM_TAG_WIDTH
)(
// Clock
input wire clk,
@ -21,16 +20,17 @@ module Vortex_axi #(
output wire [7:0] m_axi_awlen,
output wire [2:0] m_axi_awsize,
output wire [1:0] m_axi_awburst,
output wire m_axi_awlock,
output wire [1:0] m_axi_awlock,
output wire [3:0] m_axi_awcache,
output wire [2:0] m_axi_awprot,
output wire [3:0] m_axi_awqos,
output wire [3:0] m_axi_awregion,
output wire m_axi_awvalid,
input wire m_axi_awready,
// AXI write request data channel
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [AXI_STROBE_WIDTH-1:0] m_axi_wstrb,
output wire [AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
@ -47,10 +47,11 @@ module Vortex_axi #(
output wire [7:0] m_axi_arlen,
output wire [2:0] m_axi_arsize,
output wire [1:0] m_axi_arburst,
output wire m_axi_arlock,
output wire [1:0] m_axi_arlock,
output wire [3:0] m_axi_arcache,
output wire [2:0] m_axi_arprot,
output wire [3:0] m_axi_arqos,
output wire [3:0] m_axi_arregion,
output wire m_axi_arvalid,
input wire m_axi_arready,
@ -84,14 +85,9 @@ module Vortex_axi #(
wire mem_rsp_ready;
VX_axi_adapter #(
.VX_DATA_WIDTH (`VX_MEM_DATA_WIDTH),
.VX_ADDR_WIDTH (`VX_MEM_ADDR_WIDTH),
.VX_TAG_WIDTH (`VX_MEM_TAG_WIDTH),
.VX_BYTEEN_WIDTH (AXI_STROBE_WIDTH),
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_TID_WIDTH (AXI_TID_WIDTH),
.AXI_STROBE_WIDTH (AXI_STROBE_WIDTH)
.DATA_WIDTH (AXI_DATA_WIDTH),
.ADDR_WIDTH (AXI_ADDR_WIDTH),
.TAG_WIDTH (AXI_TID_WIDTH)
) axi_adapter (
.clk (clk),
.reset (reset),
@ -118,6 +114,7 @@ module Vortex_axi #(
.m_axi_awcache (m_axi_awcache),
.m_axi_awprot (m_axi_awprot),
.m_axi_awqos (m_axi_awqos),
.m_axi_awregion (m_axi_awregion),
.m_axi_awvalid (m_axi_awvalid),
.m_axi_awready (m_axi_awready),
@ -141,6 +138,7 @@ module Vortex_axi #(
.m_axi_arcache (m_axi_arcache),
.m_axi_arprot (m_axi_arprot),
.m_axi_arqos (m_axi_arqos),
.m_axi_arregion (m_axi_arregion),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_arready (m_axi_arready),

130
hw/rtl/libs/VX_axi_adapter.sv
View file

@ -2,84 +2,78 @@
`TRACING_OFF
module VX_axi_adapter #(
parameter VX_DATA_WIDTH = 512,
parameter VX_ADDR_WIDTH = (32 - $clog2(VX_DATA_WIDTH/8)),
parameter VX_TAG_WIDTH = 8,
parameter AXI_DATA_WIDTH = VX_DATA_WIDTH,
parameter AXI_ADDR_WIDTH = 32,
parameter AXI_TID_WIDTH = VX_TAG_WIDTH,
parameter VX_BYTEEN_WIDTH = (VX_DATA_WIDTH / 8),
parameter AXI_STROBE_WIDTH = (AXI_DATA_WIDTH / 8)
parameter DATA_WIDTH = 512,
parameter ADDR_WIDTH = (32 - $clog2(DATA_WIDTH/8)),
parameter TAG_WIDTH = 8
) (
input wire clk,
input wire reset,
input wire clk,
input wire reset,
// Vortex request
input wire mem_req_valid,
input wire mem_req_rw,
input wire [VX_BYTEEN_WIDTH-1:0] mem_req_byteen,
input wire [VX_ADDR_WIDTH-1:0] mem_req_addr,
input wire [VX_DATA_WIDTH-1:0] mem_req_data,
input wire [VX_TAG_WIDTH-1:0] mem_req_tag,
input wire mem_req_valid,
input wire mem_req_rw,
input wire [DATA_WIDTH/8-1:0] mem_req_byteen,
input wire [ADDR_WIDTH-1:0] mem_req_addr,
input wire [DATA_WIDTH-1:0] mem_req_data,
input wire [TAG_WIDTH-1:0] mem_req_tag,
// Vortex response
input wire mem_rsp_ready,
output wire mem_rsp_valid,
output wire [VX_DATA_WIDTH-1:0] mem_rsp_data,
output wire [VX_TAG_WIDTH-1:0] mem_rsp_tag,
output wire mem_req_ready,
input wire mem_rsp_ready,
output wire mem_rsp_valid,
output wire [DATA_WIDTH-1:0] mem_rsp_data,
output wire [TAG_WIDTH-1:0] mem_rsp_tag,
output wire mem_req_ready,
// AXI write request address channel
output wire [AXI_TID_WIDTH-1:0] m_axi_awid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [7:0] m_axi_awlen,
output wire [2:0] m_axi_awsize,
output wire [1:0] m_axi_awburst,
output wire m_axi_awlock,
output wire [3:0] m_axi_awcache,
output wire [2:0] m_axi_awprot,
output wire [3:0] m_axi_awqos,
output wire m_axi_awvalid,
input wire m_axi_awready,
output wire [TAG_WIDTH-1:0] m_axi_awid,
output wire [ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [7:0] m_axi_awlen,
output wire [2:0] m_axi_awsize,
output wire [1:0] m_axi_awburst,
output wire [1:0] m_axi_awlock,
output wire [3:0] m_axi_awcache,
output wire [2:0] m_axi_awprot,
output wire [3:0] m_axi_awqos,
output wire [3:0] m_axi_awregion,
output wire m_axi_awvalid,
input wire m_axi_awready,
// AXI write request data channel
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [AXI_STROBE_WIDTH-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
output wire [DATA_WIDTH-1:0] m_axi_wdata,
output wire [DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
// AXI write response channel
input wire [AXI_TID_WIDTH-1:0] m_axi_bid,
input wire [1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
input wire [TAG_WIDTH-1:0] m_axi_bid,
input wire [1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
// AXI read address channel
output wire [AXI_TID_WIDTH-1:0] m_axi_arid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [7:0] m_axi_arlen,
output wire [2:0] m_axi_arsize,
output wire [1:0] m_axi_arburst,
output wire m_axi_arlock,
output wire [3:0] m_axi_arcache,
output wire [2:0] m_axi_arprot,
output wire [3:0] m_axi_arqos,
output wire m_axi_arvalid,
input wire m_axi_arready,
output wire [TAG_WIDTH-1:0] m_axi_arid,
output wire [ADDR_WIDTH-1:0] m_axi_araddr,
output wire [7:0] m_axi_arlen,
output wire [2:0] m_axi_arsize,
output wire [1:0] m_axi_arburst,
output wire [1:0] m_axi_arlock,
output wire [3:0] m_axi_arcache,
output wire [2:0] m_axi_arprot,
output wire [3:0] m_axi_arqos,
output wire [3:0] m_axi_arregion,
output wire m_axi_arvalid,
input wire m_axi_arready,
// AXI read response channel
input wire [AXI_TID_WIDTH-1:0] m_axi_rid,
input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready
input wire [TAG_WIDTH-1:0] m_axi_rid,
input wire [DATA_WIDTH-1:0] m_axi_rdata,
input wire [1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready
);
localparam AXSIZE = $clog2(VX_DATA_WIDTH/8);
`STATIC_ASSERT((AXI_DATA_WIDTH == VX_DATA_WIDTH), ("invalid parameter"))
`STATIC_ASSERT((AXI_TID_WIDTH == VX_TAG_WIDTH), ("invalid parameter"))
localparam AXSIZE = $clog2(DATA_WIDTH/8);
//`UNUSED_VAR ()
@ -108,14 +102,15 @@ module VX_axi_adapter #(
// AXI write request address channel
assign m_axi_awvalid = mem_req_valid && mem_req_rw && !awvalid_ack;
assign m_axi_awid = mem_req_tag;
assign m_axi_awaddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE;
assign m_axi_awaddr = ADDR_WIDTH'(mem_req_addr) << AXSIZE;
assign m_axi_awlen = 8'b00000000;
assign m_axi_awsize = 3'(AXSIZE);
assign m_axi_awburst = 2'b00;
assign m_axi_awlock = 1'b0;
assign m_axi_awlock = 2'b00;
assign m_axi_awcache = 4'b0;
assign m_axi_awprot = 3'b0;
assign m_axi_awprot = 3'b0;
assign m_axi_awqos = 4'b0;
assign m_axi_awregion = 4'b0;
// AXI write request data channel
assign m_axi_wvalid = mem_req_valid && mem_req_rw && !wvalid_ack;
@ -131,14 +126,15 @@ module VX_axi_adapter #(
// AXI read request channel
assign m_axi_arvalid = mem_req_valid && !mem_req_rw;
assign m_axi_arid = mem_req_tag;
assign m_axi_araddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE;
assign m_axi_araddr = ADDR_WIDTH'(mem_req_addr) << AXSIZE;
assign m_axi_arlen = 8'b00000000;
assign m_axi_arsize = 3'(AXSIZE);
assign m_axi_arburst = 2'b00;
assign m_axi_arlock = 1'b0;
assign m_axi_arlock = 2'b00;
assign m_axi_arcache = 4'b0;
assign m_axi_arprot = 3'b0;
assign m_axi_arqos = 4'b0;
assign m_axi_arregion = 4'b0;
// AXI read response channel
assign mem_rsp_valid = m_axi_rvalid;

4
hw/syn/altera/opae/Makefile
View file

@ -3,7 +3,7 @@ BUILD_DIR ?= build
RTL_DIR = ../../../rtl
DPI_DIR = ../../../dpi
AFU_DIR = ../../../afu/opae
IP_DIR = ../../../ip/altera/$(DEVICE_FAMILY)
IP_DIR = ../../../ip/altera
ifeq ($(shell which qsub-synth),)
RUN_SYNTH=$(OPAE_PLATFORM_ROOT)/bin/run.sh > build.log 2>&1 &
@ -61,7 +61,7 @@ FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit
ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(IP_DIR)
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(IP_DIR) -I$(IP_DIR)/$(DEVICE_FAMILY)
RTL_INCLUDE += $(FPU_INCLUDE) $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)
CFLAGS += $(RTL_INCLUDE)

3
hw/syn/altera/quartus/common.mk
View file

@ -1,16 +1,15 @@
RTL_DIR = ../../../../../rtl
AFU_DIR = ../../../../../afu/opae
THIRD_PARTY_DIR = ../../../../../../third_party
IP_DIR = ../../../../../ip/altera;../../../../../ip/altera/$(DEVICE_FAMILY)
ifeq ($(DEVICE_FAMILY), stratix10)
FAMILY = "Stratix 10"
DEVICE = 1SX280HN2F43E2VG
IP_DIR = ../../../../../ip/altera/stratix10
endif
ifeq ($(DEVICE_FAMILY), arria10)
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
IP_DIR = ../../../../../ip/altera/arria10
endif
CONFIGS += -set "NDEBUG"

3
hw/syn/xilinx/README.md
View file

@ -1,2 +1,5 @@
## Xilinx Build and Ecosystem Setup
make all TARGET=hw_emu PLATFORM=xilinx_u280_xdma_201920_3 > build.log 2>&1
vivado -mode batch -source scripts/gen_ips.tcl -tclargs ../../../ip/xilinx/xilinx_u280_xdma_201920_3

192
hw/syn/xilinx/xrt/Makefile
View file

@ -1,69 +1,9 @@
#
# Copyright 2019-2021 Xilinx, Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# makefile-generator v1.0.3
#
# Points to top directory of Git repository
MK_PATH := $(abspath $(lastword $(MAKEFILE_LIST)))
COMMON_REPO ?= $(shell bash -c 'export MK_PATH=$(MK_PATH); echo $${MK_PATH%rtl_kernels/rtl_user_managed/*}')
PWD = $(shell readlink -f .)
XF_PROJ_ROOT = $(shell readlink -f $(COMMON_REPO))
KERNEL_NAME = vortex_kernel
.PHONY: help
####################### Checking if PLATFORM in allowlist #####################
PLATFORM_BLOCKLIST += nodma
ifneq ($(TARGET),$(findstring $(TARGET), hw hw_emu))
$(error Application supports only hw hw_emu TARGET. Please use the target for running the application)
endif
PLATFORM ?= xilinx_u50_gen3x16_xdma_201920_3
DEV_ARCH := $(shell platforminfo -p $(PLATFORM) | grep 'FPGA Family' | sed 's/.*://' | sed '/ai_engine/d' | sed 's/^[[:space:]]*//')
CPU_TYPE := $(shell platforminfo -p $(PLATFORM) | grep 'CPU Type' | sed 's/.*://' | sed '/ai_engine/d' | sed 's/^[[:space:]]*//')
ifeq ($(CPU_TYPE), cortex-a9)
HOST_ARCH := aarch32
else ifneq (,$(findstring cortex-a, $(CPU_TYPE)))
HOST_ARCH := aarch64
else
HOST_ARCH := x86
endif
ifeq ($(DEV_ARCH), zynquplus)
ifeq ($(HOST_ARCH), aarch64)
include makefile_zynqmp.mk
else
include makefile_us_alveo.mk
endif
else ifeq ($(DEV_ARCH), zynq)
include makefile_zynq7000.mk
else ifeq ($(DEV_ARCH), versal)
ifeq ($(HOST_ARCH), x86)
include makefile_versal_alveo.mk
else
include makefile_versal_ps.mk
endif
else
include makefile_us_alveo.mk
endif
################################ Help Section #################################
help:
help::
$(ECHO) "Makefile Usage:"
$(ECHO) " make all TARGET=<sw_emu/hw_emu/hw> PLATFORM=<FPGA platform> EDGE_COMMON_SW=<rootfs and kernel image path>"
$(ECHO) " Command to generate the design for specified Target and Shell."
$(ECHO) " make all TARGET=<sw_emu/hw_emu/hw> PLATFORM=<FPGA platform>"
$(ECHO) " Command to generate the design for specified Target and Device."
$(ECHO) ""
$(ECHO) " make clean "
$(ECHO) " Command to remove the generated non-hardware files."
@ -71,20 +11,118 @@ help:
$(ECHO) " make cleanall"
$(ECHO) " Command to remove all the generated files."
$(ECHO) ""
$(ECHO) " make test PLATFORM=<FPGA platform>"
$(ECHO) " Command to run the application. This is same as 'run' target but does not have any makefile dependency."
$(ECHO) ""
$(ECHO) " make sd_card TARGET=<sw_emu/hw_emu/hw> PLATFORM=<FPGA platform> EDGE_COMMON_SW=<rootfs and kernel image path>"
$(ECHO) " Command to prepare sd_card files."
$(ECHO) ""
$(ECHO) " make run TARGET=<sw_emu/hw_emu/hw> PLATFORM=<FPGA platform> EDGE_COMMON_SW=<rootfs and kernel image path>"
$(ECHO) " make check TARGET=<sw_emu/hw_emu/hw> PLATFORM=<FPGA platform>"
$(ECHO) " Command to run application in emulation."
$(ECHO) ""
$(ECHO) " make build TARGET=<sw_emu/hw_emu/hw> PLATFORM=<FPGA platform> EDGE_COMMON_SW=<rootfs and kernel image path>"
$(ECHO) " Command to build xclbin application."
$(ECHO) " make run_nimbix PLATFORM=<FPGA platform>"
$(ECHO) " Command to run application on Nimbix Cloud."
$(ECHO) ""
$(ECHO) " make host EDGE_COMMON_SW=<rootfs and kernel image path>"
$(ECHO) " Command to build host application."
$(ECHO) " EDGE_COMMON_SW is required for SoC shells. Please download and use the pre-built image from - "
$(ECHO) " https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html"
$(ECHO) " make aws_build PLATFORM=<FPGA platform>"
$(ECHO) " Command to build AWS xclbin application on AWS Cloud."
$(ECHO) ""
TARGET := hw
PLATFORM :=
XCLBIN := ./xclbin
VPP := $(XILINX_VITIS)/bin/v++
CP = cp -rf
RMDIR = rm -rf
ECHO:= @echo
XO_CONTAINER = $(XCLBIN)/vortex_afu.$(TARGET).xo
XCLBIN_CONTAINER = $(XCLBIN)/vortex_afu.$(TARGET).xclbin
# Kernel compiler global settings
CLFLAGS += -t $(TARGET) --platform $(PLATFORM) --save-temps
##########################################################################
# The below commands generate a XO file from a pre-exsisitng RTL kernel.
###########################################################################
VIVADO := $(XILINX_VIVADO)/bin/vivado
$(XO_CONTAINER): ./scripts/package_kernel.tcl ./scripts/gen_xo.tcl
mkdir -p $(XCLBIN)
$(VIVADO) -mode batch -source scripts/gen_xo.tcl -tclargs $(XO_CONTAINER) vortex_afu $(TARGET) $(PLATFORM)
###########################################################################
#END OF GENERATION OF XO
##########################################################################
.PHONY: all clean cleanall emconfig
all: check-devices $(XCLBIN_CONTAINER) emconfig
# Building kernel
$(XCLBIN_CONTAINER): $(XO_CONTAINER)
mkdir -p $(XCLBIN)
$(VPP) $(CLFLAGS) $(LDCLFLAGS) -lo $(XCLBIN_CONTAINER) $(XO_CONTAINER)
emconfig: $(XCLBIN)/emconfig.json
$(XCLBIN)/emconfig.json:
emconfigutil --platform $(PLATFORM) --od $(XCLBIN)
# Cleaning stuff
clean:
-$(RMDIR) $(XCLBIN)/{*sw_emu*,*hw_emu*}
-$(RMDIR) TempConfig system_estimate.xtxt *.rpt
-$(RMDIR) src/*.ll _v++_* .Xil emconfig.json dltmp* xmltmp* *.log *.jou
cleanall: clean
-$(RMDIR) $(XCLBIN)
-$(RMDIR) _x.*
-$(RMDIR) ./tmp_kernel_pack* ./packaged_kernel* _x/
#######################################################################
# RTL Kernel only supports Hardware and Hardware Emulation.
# THis line is to check that
#########################################################################
ifneq ($(TARGET),$(findstring $(TARGET), hw hw_emu))
$(warning WARNING:Application supports only hw hw_emu TARGET. Please use the target for running the application)
endif
###################################################################
#check the devices avaiable
########################################################################
check-devices:
ifndef PLATFORM
$(error PLATFORM not set. Please set the PLATFORM properly and rerun. Run "make help" for more details.)
endif
############################################################################
# check the VITIS environment
#############################################################################
ifndef XILINX_VITIS
$(error XILINX_VITIS variable is not set, please set correctly and rerun)
endif
#################################################################
# Enable profiling if needed
#####################################################################a
REPORT := no
PROFILE := no
DEBUG := no
#'estimate' for estimate report generation
#'system' for system report generation
ifneq ($(REPORT), no)
CLFLAGS += --report estimate
CLLDFLAGS += --report system
endif
#Generates profile summary report
ifeq ($(PROFILE), yes)
LDCLFLAGS += --profile_kernel data:all:all:all
endif
#Generates debug summary report
ifeq ($(DEBUG), yes)
CLFLAGS += --dk protocol:all:all:all
endif

4
hw/syn/xilinx/xrt/scripts/gen_xo.tcl
View file

@ -20,7 +20,7 @@ if { $::argc != 5 } {
exit
}
set xoname [lindex $::argv 0]
set xoname [lindex $::argv 0]
set krnl_name [lindex $::argv 1]
set target [lindex $::argv 2]
set xpfm_path [lindex $::argv 3]
@ -34,4 +34,4 @@ if {[file exists "${xoname}"]} {
file delete -force "${xoname}"
}
package_xo -ctrl_protocol user_managed -xo_path ${xoname} -kernel_name krnl_vadd_rtl -ip_directory ./packaged_kernel_${suffix}
package_xo -ctrl_protocol user_managed -xo_path ${xoname} -kernel_name vortex_afu -ip_directory ./packaged_kernel_${suffix}

27
hw/syn/xilinx/xrt/scripts/package_kernel.tcl
View file

@ -21,9 +21,10 @@ set path_to_hdl_ip "../../../ip/xilinx/alveo"
set path_to_packaged "./packaged_kernel_${suffix}"
set path_to_tmp_project "./tmp_kernel_pack_${suffix}"
create_project -force kernel_pack $path_to_tmp_project
add_files -fileset sources_1 -verbose [glob $path_to_hdl_vx $path_to_hdl_afu $path_to_hdl_ip]
set_property verilog_define {SYNTHESIS=1 NDEBUG=1} [get_filesets sources_1]
create_project -force kernel_pack $path_to_tmp_project
add_files -verbose [glob globals.vh $path_to_hdl_vx $path_to_hdl_afu $path_to_hdl_ip]
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
ipx::package_project -root_dir $path_to_packaged -vendor xilinx.com -library RTLKernel -taxonomy /KernelIP -import_files -set_current false
@ -104,27 +105,9 @@ set reg [::ipx::add_register "IP_ISR" $addr_block]
set_property address_offset 0x00C $reg
set_property size 32 $reg
set reg [::ipx::add_register -quiet "a" $addr_block]
set reg [::ipx::add_register -quiet "DCR" $addr_block]
set_property address_offset 0x010 $reg
set_property size [expr {8*8}] $reg
set regparam [::ipx::add_register_parameter -quiet {ASSOCIATED_BUSIF} $reg]
set_property value m_axi_gmem $regparam
set reg [::ipx::add_register -quiet "b" $addr_block]
set_property address_offset 0x01C $reg
set_property size [expr {8*8}] $reg
set regparam [::ipx::add_register_parameter -quiet {ASSOCIATED_BUSIF} $reg]
set_property value m_axi_gmem $regparam
set reg [::ipx::add_register -quiet "c" $addr_block]
set_property address_offset 0x028 $reg
set_property size [expr {8*8}] $reg
set regparam [::ipx::add_register_parameter -quiet {ASSOCIATED_BUSIF} $reg]
set_property value m_axi_gmem $regparam
set reg [::ipx::add_register -quiet "length_r" $addr_block]
set_property address_offset 0x034 $reg
set_property size [expr {4*8}] $reg
set_property slave_memory_map_ref "s_axi_control" [::ipx::get_bus_interfaces -of $core "s_axi_control"]

3
tests/regression/draw3d/Makefile
View file

@ -14,8 +14,9 @@ OPTS ?=
VX_CLANG_FLAGS = --sysroot=${RISCV_TOOLCHAIN_PATH}/riscv32-unknown-elf
VX_CLANG_FLAGS += -Xclang -target-feature -Xclang +vortex
VX_CLANG_FLAGS += -Wl,-L$(RISCV_TOOLCHAIN_PATH)/lib/gcc/riscv32-unknown-elf/9.2.0 -I$(RISCV_TOOLCHAIN_PATH)/riscv32-unknown-elf/include/c++/9.2.0/riscv32-unknown-elf -I$(RISCV_TOOLCHAIN_PATH)/riscv32-unknown-elf/include/c++/9.2.0
VX_CLANG_FLAGS += -I$(RISCV_TOOLCHAIN_PATH)/riscv32-unknown-elf/include/c++/9.2.0/riscv32-unknown-elf -I$(RISCV_TOOLCHAIN_PATH)/riscv32-unknown-elf/include/c++/9.2.0
VX_CLANG_FLAGS += --rtlib=libgcc
VX_CLANG_FLAGS += -Wl,-L$(RISCV_TOOLCHAIN_PATH)/lib/gcc/riscv32-unknown-elf/9.2.0
VX_CC = $(LLVM_PREFIX)/bin/clang
VX_CXX = $(LLVM_PREFIX)/bin/clang++ $(VX_CLANG_FLAGS)