34 commits

Author	SHA1	Message	Date
Hanran Wu	ea9560b33b	merge	2024-08-23 17:44:24 -04:00
Blaise Tine	9dbff0e77c	makefile clean-all	2024-05-27 20:03:16 -07:00
Blaise Tine	60107cf2b6	XRT runtime and simulation support for Vortex AFU (incomplete)	2024-05-11 17:43:49 -07:00
Blaise Tine	486cd0b866	minor update	2024-03-30 22:45:31 -07:00
Blaise Tine	d47cccc157	Vortex 2.0 changes: ... + Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes	2023-10-19 20:51:22 -07:00
Santosh Srivatsan	7e3a2fdb0f	Modifications to allow 64-bit riscv tests to run on travis CI	2022-01-27 15:55:19 -05:00
Santosh Srivatsan	91c22a2592	Fixed some riscv-tests	2022-01-22 12:54:10 -05:00
Santosh Srivatsan	d762d401cd	Added 64-bit linker script	2022-01-11 17:22:16 -05:00
Santosh Srivatsan	d7e2a6b3b1	Minor update	2021-12-18 16:27:29 -05:00
Santosh Srivatsan	d14e05e748	Removed all instances of my username \'ssrivatsan8\' and un-did the changes to vx_start.S	2021-12-13 20:01:11 -05:00
Santosh Srivatsan	5edb9098ce	Merge branch 'simx64'	2021-12-10 21:48:29 -05:00
Santosh Raghav Srivatsan	e6eda67d0c	Modified RV32F instructions to support 64-bit register file and added RV64F ISA extension	2021-12-06 18:55:13 -05:00
Santosh Raghav Srivatsan	30a0d34151	Fixed Makefile	2021-12-05 15:55:43 -05:00
Santosh Raghav Srivatsan	3784da0d2f	riscv-tests work on simx	2021-12-01 19:41:16 -05:00
Santosh Raghav Srivatsan	64d47f3637	Added support for RV64I instructions	2021-11-27 12:33:30 -05:00
Blaise Tine	b995843a5b	cocogfx fixes and refactoring	2021-11-25 13:58:09 -05:00
Blaise Tine	18762dffce	fixes: texture unit mem access sometimes going to smem, bilinear texture filtering; new: cache req_id,	2021-11-24 00:00:17 -05:00
Santosh Raghav Srivatsan	d1892bd6ec	Added support for a few RV64I instructions	2021-11-11 13:35:14 -05:00
Blaise Tine	b8682f56ac	softfloat library integration	2021-10-10 13:20:50 -07:00
Blaise Tine	47d317f17a	vx_serial runtime API	2021-06-28 05:43:36 -04:00
Blaise Tine	3cc1190cd7	CSRs I/O refactoring	2021-06-11 03:08:07 -07:00
Blaise Tine	778453e43f	remove unused code from kernel binaries, spawn_kernel optimization using shift instead of division	2021-02-04 17:35:57 -05:00
Blaise Tine	b047f589d6	runtime instrinsics refactoring using RISC-V custom instruction assmebly directives	2021-02-04 15:15:20 -05:00
Blaise Tine	f6f95e0c46	mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL	2020-09-19 14:45:42 -04:00
Blaise Tine	8a306de02d	runtime static library	2020-06-27 14:13:13 -04:00
Blaise Tine	106d707024	verilator suppor for opae (partial)	2020-06-03 06:22:49 -04:00
Blaise Tine	81745f08c9	added config.vh	2020-04-16 07:49:19 -04:00
Blaise Tine	12dc4d6874	refactoring fixes	2020-04-14 19:39:59 -04:00
Blaise Tine	fc155e1223	project directories reorganization	2020-04-14 06:35:20 -04:00
wgulian3	f126a23114	Generate define overrides based on env vars for C and Verilog. ... gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.	2020-03-26 04:08:43 -04:00
felsabbagh3	9a0c5e0dbc	Removed kernel	2019-11-07 00:15:07 -05:00
felsabbagh3	fcd3bbc4a1	old tb	2019-11-05 22:57:05 -05:00
felsabbagh3	95d8a251db	runtime tests	2019-11-02 10:35:20 -04:00
felsabbagh3	46b09028d0	Added runtime (kernel 2.0)	2019-10-30 23:40:01 -04:00