325 commits

Author	SHA1	Message	Date
Blaise Tine	43ae82e788	vlsim fix, verilator fst trace, use ram optimization	2020-10-25 16:40:50 -07:00
Blaise Tine	e9d1754990	Merge branch 'master' of https://github.com/vortexgpgpu/vortex-dev	2020-10-20 11:49:35 -04:00
Blaise Tine	e6466b887c	minor update	2020-10-20 08:45:21 -07:00
Blaise Tine	7529f72c5d	fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags	2020-10-20 05:32:55 -07:00
Blaise Tine	32da50816f	scope refactoring: adding modules definitions to VCD trace	2020-10-12 23:26:02 -04:00
Carter René Montgomery	a83048b3bd	Comments	2020-10-06 14:50:56 -04:00
Carter René Montgomery	1f4af4777c	Comments	2020-10-06 14:35:46 -04:00
Carter René Montgomery	d2ab8d3cc6	Added comments to prep for cache presentation	2020-10-05 14:49:47 -04:00
Blaise Tine	4e1007e5b2	scope refactoring	2020-10-03 18:53:21 -04:00
Blaise Tine	f6f95e0c46	mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL	2020-09-19 14:45:42 -04:00
Blaise Tine	42e3b6c45d	fixed lmp_mult parameters, ram init filepath	2020-09-04 07:51:46 -07:00
Blaise Tine	31ffbe0d6a	clean up 'stage_1_cycles' from cache	2020-09-01 03:39:03 -07:00
Blaise Tine	af84e01856	minor update	2020-08-31 06:17:49 -07:00
Blaise Tine	0a0b28aac0	minor update - 206-214 mhz	2020-08-29 05:14:08 -07:00
Blaise Tine	f292e5003d	quartus build fixes	2020-08-23 22:04:46 -07:00
Blaise Tine	0b355f228e	ibuffer addition	2020-08-22 00:22:04 -07:00
Blaise Tine	6c12391338	pipeline refactoring - fmax >= 222 mhz	2020-08-14 21:50:14 -07:00
Blaise Tine	65415d2bbc	getting dogfood tests passing on Verilator!	2020-08-09 18:13:12 -04:00
Blaise Tine	cd29362d10	fixed FPU handshake, optimized writeback's critical path	2020-08-07 10:11:54 -07:00
Blaise Tine	31ee824862	merged fpu_port branch	2020-07-31 17:13:22 -04:00
Blaise Tine	4bdab8903e	merge	2020-07-31 16:49:59 -04:00
Blaise Tine	c9755a0c48	lkg build with pipeline + FPU fixes	2020-07-31 09:29:44 -04:00
Blaise Tine	c2dd0a8b39	modelsim fixes && pipeline optimization	2020-07-28 14:20:23 -07:00
Blaise Tine	7c86b68977	pipeline refactoring: centralized issue buffer	2020-07-26 11:21:08 -04:00
Blaise Tine	1f63f9da25	new fpu implementation	2020-07-24 00:00:37 -04:00
Blaise Tine	dc7efbcfb4	pipeline refactoring	2020-07-21 05:22:47 -04:00
Blaise Tine	577a5791dc	pipeline refactoring	2020-07-20 08:04:04 -04:00
Blaise Tine	25f66e6490	pipeline refactoring	2020-07-19 05:03:47 -04:00
trmontgomery	ed3a0cfa4d	added rsp map	2020-07-19 00:08:09 -04:00
Blaise Tine	bdfacf709c	yosys synthesis refactoring	2020-07-10 18:56:41 -04:00
Blaise Tine	77c3b2d45f	lsu_unit refactoring to reduce critical path	2020-07-10 11:23:34 -07:00
Blaise Tine	582a00d690	adding OPAE CSR support	2020-06-30 10:05:57 -07:00
felsabbagh3	14e4fd95b7	Don't allow snrq scheduling if there's a valid reqq entry (Event if it can't be scheduled)	2020-06-29 00:03:36 -07:00
felsabbagh3	21566cdcd7	Fixed Single Core with Optimizations	2020-06-28 19:38:36 -07:00
felsabbagh3	567376971e	Added dram_fill_req_fast which is used to stall bank pipeline	2020-06-28 15:22:36 -07:00
felsabbagh3	ffb760cf73	Optimized cache writeback path by 1) VX_fair_arbiter and 2) Added a wb register between LSU and WB arbiter	2020-06-28 14:27:47 -07:00
felsabbagh3	c95d3cb22b	Added cache critical path optimizations	2020-06-27 16:12:22 -07:00
Blaise Tine	baf7d3bb92	minor update	2020-06-27 17:46:45 -04:00
Blaise Tine	bc0c65dce7	Merge branch 'master' of https://github.gatech.edu/casl/Vortex	2020-06-27 13:56:44 -07:00
Blaise Tine	8302641510	fpga fixes	2020-06-27 14:03:20 -07:00
Blaise Tine	8a306de02d	runtime static library	2020-06-27 14:13:13 -04:00
Blaise Tine	0a01385a2c	few updates	2020-06-23 09:28:24 -07:00
Blaise Tine	d3440de403	round robin arbiter + auto buffered queue + fixed dcache arbiter	2020-06-20 17:56:04 -04:00
Blaise Tine	68d9fc9a75	driver basic test and demo test refactoring	2020-06-19 09:12:07 -07:00
Blaise Tine	d6b0ef2b3c	scope refactoring + snoop invalidate	2020-06-12 00:04:31 -07:00
Blaise Tine	c4f2488dbe	Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis ... t # the commit.	2020-06-04 15:44:40 -07:00
Blaise Tine	4e0e710182	OPAE rtl fixes	2020-06-04 15:44:03 -07:00
Blaise Tine	171d46b501	fix l2 cache issues	2020-06-04 18:34:14 -04:00
Blaise Tine	ea890b457d	fixed msrq regression	2020-06-03 17:22:24 -04:00
Blaise Tine	04fc34b848	minor update	2020-06-03 03:05:45 -07:00