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Author	SHA1	Message	Date
felsabbagh3	9d8273afe4	Finished Cache Integration	2019-10-22 06:02:08 -04:00
felsabbagh3	b7af8c3f34	Integrated Shared Memory	2019-10-22 05:03:47 -04:00
felsabbagh3	1bfafca896	Cleanup before integration	2019-10-22 03:03:17 -04:00
felsabbagh3	b3f464dd89	Barriers impl + tested	2019-10-22 01:47:39 -04:00
felsabbagh3	31d3d51392	WSPAWN imp + tested	2019-10-21 23:35:53 -04:00
felsabbagh3	c21e400f9f	Readded IPDOM stack + SPLIT/Join tested	2019-10-21 21:26:21 -04:00
felsabbagh3	b6375e76de	Readded IPDOM stack + SPLIT/Join tested	2019-10-21 21:24:49 -04:00
Lingjun Zhu	eeb0a321a8	Finished synthesis with no optimization, cell count increasts to 100k	2019-10-21 17:53:51 -04:00
Lingjun Zhu	e2cd8102eb	Uncommented the necessary line about write_bit_mask on VX_gpr.v again, try synthesizing	2019-10-21 17:09:51 -04:00
felsabbagh3	0672389edc	fix	2019-10-21 12:16:17 -04:00
felsabbagh3	ce49e2f223	proper init warp scheduelr	2019-10-21 12:13:34 -04:00
felsabbagh3	8050419511	added begin	2019-10-21 12:06:10 -04:00
felsabbagh3	85004899bd	added reset to ws	2019-10-21 12:03:07 -04:00
felsabbagh3	99586279d9	always fix stack	2019-10-21 11:49:10 -04:00
felsabbagh3	292c792339	generic stack reset	2019-10-21 11:45:51 -04:00
felsabbagh3	4bfdbb5188	reset posedge	2019-10-21 11:34:12 -04:00
felsabbagh3	fd876144f5	.tcl mod	2019-10-21 11:27:01 -04:00
felsabbagh3	49b139d512	fix	2019-10-21 11:24:45 -04:00
felsabbagh3	121a985d12	Reset to Generic Register	2019-10-21 11:21:13 -04:00
felsabbagh3	bab1852a99	Added Split/Join - not tested	2019-10-21 03:03:15 -04:00
felsabbagh3	84f5ccb484	Added CSR TID/WID reads	2019-10-21 02:10:05 -04:00
Lingjun Zhu	405926f66f	Generated memory blocks for data cache (data), data cache (tag), shared memory	2019-10-20 14:52:28 -04:00
felsabbagh3	797801ebae	CENA/CENB Modifications + Still not working	2019-10-19 14:52:57 -04:00
Lingjun Zhu	93531715bb	Created a testbench and simulated the read/write of the register file	2019-10-18 22:55:34 -04:00
felsabbagh3	4cae140ac1	Mem technology compiling but still reading all zeros	2019-10-18 16:45:42 -04:00
felsabbagh3	f7d826593f	TMC working and tested	2019-10-18 16:09:06 -04:00
felsabbagh3	f7b55427b4	Added ISA2 infrastructure with bugs	2019-10-18 05:21:32 -04:00
felsabbagh3	629ed3f8f9	Before ISA2.0	2019-10-18 04:15:34 -04:00
felsabbagh3	559c64cb36	Cleanup	2019-10-18 02:20:38 -04:00
felsabbagh3	505bbc20c8	Removed FWD	2019-10-18 02:01:39 -04:00
felsabbagh3	6b729fd2ea	minor	2019-10-18 01:46:38 -04:00
felsabbagh3	ccbb2acab5	LSU+EXU minor	2019-10-17 22:38:09 -04:00
felsabbagh3	6779d0fade	Instruction Multiplex LSU/EXU 1 cycle DONE	2019-10-17 22:29:21 -04:00
Lingjun Zhu	84d321a517	Create the memory blocks with CLN28HPM	2019-10-17 15:38:48 -04:00
Lingjun Zhu	d164ebfbc6	Added log file of synthesis, too many registers are removed	2019-10-17 14:25:54 -04:00
Lingjun Zhu	a4d6ada16d	Fixed the issues of memory during synthesis	2019-10-17 14:18:52 -04:00
Shim	6cfb44396e	Merge branch 'master' of https://github.gatech.edu/casl/Vortex	2019-10-17 14:01:00 -04:00
Shim	78e4067013	added log file	2019-10-17 14:00:22 -04:00
felsabbagh3	62db9ae691	minor	2019-10-17 12:04:06 -04:00
Shim	0bea82a2c3	added tcl file	2019-10-17 11:55:18 -04:00
felsabbagh3	9bf186fc77	minor	2019-10-17 11:51:11 -04:00
felsabbagh3	e8a43fa7a9	minor	2019-10-17 11:44:19 -04:00
felsabbagh3	10fbb53c38	minor	2019-10-17 11:29:40 -04:00
felsabbagh3	33e20a2d80	minor	2019-10-17 11:25:29 -04:00
felsabbagh3	b08297eafb	minor	2019-10-17 11:04:06 -04:00
felsabbagh3	7fd5312b67	minor	2019-10-17 10:50:36 -04:00
felsabbagh3	95047fcadc	Rename Stage that removes the need for forwarding	2019-10-17 00:48:54 -04:00
felsabbagh3	9a9afbbb6b	Updated makefile	2019-10-16 19:56:11 -04:00
felsabbagh3	0690043a43	Still giving sc_time_stamp error	2019-10-16 19:45:21 -04:00
felsabbagh3	8bc3b8b0a5	Need to link SystemC for sc_time_stamp()	2019-10-14 23:25:14 -04:00