tinebp
fbe8538573
TPU updates
2025-02-03 12:46:09 -08:00
tinebp
22398c991d
ramulator memory addressing bug fix + platform memory refactoring
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2025-01-26 06:28:51 -08:00
tinebp
704f525fd6
memory mem_coalescer miss perf counter
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RTL perf counters refactoring
2024-12-26 08:00:36 -08:00
tinebp
a98d2e24e5
rtlsim multibanks
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2024-12-16 22:10:57 -08:00
tinebp
115ff2b599
minor fixes
2024-12-05 22:38:04 -08:00
tinebp
6bbcd4ebaf
vector updates with clang formatting
2024-12-05 15:55:57 -08:00
tinebp
6b23d290c3
vector ISA updates
2024-12-05 14:43:51 -08:00
tinebp
5891a1e592
Merge branch 'master' into riscv-vector-isa-simx-clean
2024-12-05 10:17:05 -08:00
tinebp
3ace9bbeda
minor updates
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2024-12-04 06:00:19 -08:00
MichaelJSr
073e0ddd10
Adds the riscv vector extension into simx
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Added vector regression test to ci.yml
2024-11-27 23:22:22 -08:00
jaewon-lee-github
bbc02cc013
merged with master
2024-10-03 13:44:39 -04:00
Blaise Tine
b634f9f47d
count_leading_zeros fix
2024-09-28 20:15:03 -07:00
Blaise Tine
a9a5ded030
bitmanip logceil fix
2024-09-23 23:54:43 -07:00
Blaise Tine
a80be895ba
fixed compiler errors
2024-09-23 03:05:46 -07:00
Blaise Tine
b8199decf4
opaesim and xrtsim multi-bank memory support
2024-09-22 03:54:40 -07:00
Blaise Tine
a37309c6b0
xrtsim implementation
2024-09-19 04:24:20 -07:00
Jaewon Lee
e91eb4aed4
merge from master branch
2024-09-12 10:32:02 -04:00
Hanran Wu
ea9560b33b
merge
2024-08-23 17:44:24 -04:00
tinebp
6c607d32fe
Merge pull request #169 from sij814/simx
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simx HBM initial implementation
2024-08-17 20:24:37 -07:00
donghanyuan
1a9a04ac76
replace local static allocator to global static
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Ensure MemoryPool construct before SimPlatform,
thus MemoryPool destruct after SimPlatform.
Avoid use-after-free issue clearing events_ of SimPlatform
after SimPortEvent's allocator is destructed.
2024-08-13 18:13:41 +08:00
sij814
47427ab22e
regression test with source_id 0
2024-08-12 16:22:30 -07:00
sij814
bab9496117
debugging segmentation fault with 8 clusters
2024-08-12 03:52:48 -07:00
sij814
de81baaabf
hbm for vortex 2.2
2024-08-12 02:52:47 -07:00
Blaise Tine
50b12ef754
fixed memory block size configuration
2024-08-06 12:46:19 -07:00
Blaise Tine
2bc8a881b6
fixed trace log formatting
2024-07-30 12:05:36 -07:00
Blaise Tine
60f7786e17
BitVector class bug fixes
2024-07-23 09:40:20 -07:00
Blaise Tine
95f59d23a8
simx memory coalescer bug fix
2024-07-23 00:02:43 -07:00
Blaise Tine
24e8e91a94
DramSim fix
2024-07-22 03:37:10 -07:00
Blaise Tine
fb141ae522
Ramulator 2.0 with HBM 2.0 support
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Verilator 5.0 support
SimX C++17 requirement
2024-07-21 06:57:13 -07:00
Jaewon Lee
c13e02b19f
Change STARTUP_ADDR from 0x40000000 to 0x80000000(32b) and 0x180000000(64b)
2024-06-30 03:10:36 -04:00
Jaewon Lee
ccbb2243cc
fixed compile error
2024-06-30 00:54:22 -04:00
Jaewon Lee
3caeeeea13
satp_ is not set, then we skip VAT
2024-06-30 00:35:26 -04:00
Jaewon Lee
d531fa6b26
64bit support
2024-06-29 17:43:20 -04:00
Jaewon Lee
02091f3d44
Merge Vortex 2.2
2024-06-22 23:55:01 -04:00
Jaewon Lee
862997fc94
Virtual Memory Support
2024-06-19 01:52:22 -04:00
Jaewon Lee
cfcece940e
Merge Austin's code (Preliminary)
2024-06-19 01:36:26 -04:00
Hanran Wu
2b426693f5
expand MemoryUnit class defs and add some tlb-related functions
2024-06-19 01:09:56 -04:00
Blaise Tine
99eaaf6189
uuid_gen cleanup
2024-06-08 01:57:38 -07:00
Blaise Tine
aea1d2c8eb
minor updates to the build system
2024-04-30 16:27:20 -07:00
Blaise Tine
9df25ff48f
minor update
2024-04-28 04:42:22 -07:00
Blaise Tine
db0f0fd353
runtime API refactoring to support memory reservation and protection
2024-04-28 04:23:00 -07:00
Blaise Tine
ac669a30ca
UUID refactoring
2024-04-14 22:01:03 -07:00
Blaise Tine
840ced22a9
simx refactoring - emulation vs simulation discrete separation
2024-03-12 00:23:42 -07:00
Blaise Tine
ff6f33acff
simx refactoring: simobject::push(), instr_trace, FUtype, pending_instrs_
2024-03-11 15:39:49 -07:00
Blaise Tine
d47cccc157
Vortex 2.0 changes:
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+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
2023-10-19 20:51:22 -07:00
Blaise Tine
1bd25acb0b
cmov
2022-02-05 17:58:12 -05:00
Santosh Srivatsan
b7e5a83ba3
Merged branch xlen-parameterization into staging
2022-02-05 13:47:42 -05:00
Blaise Tine
140124b423
additional bug fixes
2022-02-05 07:42:50 -05:00
Blaise Tine
5fbace9fa0
fixed several bugs and refactor memory access
2022-02-04 17:50:19 -05:00
Blaise Tine
cf2a0a5f39
code refactoring
2022-02-04 00:07:24 -05:00
