11 commits

Author	SHA1	Message	Date
Blaise Tine	fe5112b6c1	minor updates	2021-09-05 23:05:21 -07:00
Blaise Tine	31b3e380dc	minor update	2021-02-15 09:23:40 -08:00
Blaise Tine	8775f63ec4	lkg build rollout with 16cores optimization on arria10	2021-01-24 16:49:22 -08:00
Blaise Tine	4bbd7bf408	performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,	2020-12-19 02:45:06 -08:00
Blaise Tine	e0905f8352	minor update	2020-12-09 05:34:27 -08:00
Blaise Tine	c3ec4c9e90	minor update	2020-12-03 09:30:59 -08:00
Blaise Tine	1c9445745f	fp_noncomp fixes	2020-08-23 16:53:28 -07:00
Blaise Tine	0b355f228e	ibuffer addition	2020-08-22 00:22:04 -07:00
Blaise Tine	6c12391338	pipeline refactoring - fmax >= 222 mhz	2020-08-14 21:50:14 -07:00
Blaise Tine	a70562d386	set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18	2020-06-29 08:03:19 -07:00
Blaise Tine	68d9fc9a75	driver basic test and demo test refactoring	2020-06-19 09:12:07 -07:00

Renamed from hw/syn/quartus/pipeline/project.sdc (Browse further)