15 commits

Author	SHA1	Message	Date
Blaise Tine	abe32ed553	cache optimization - moved read requests to stage1 and eliminating stage3	2020-12-31 07:40:58 -08:00
Blaise Tine	d956e268b9	adding new performance counters (banks utilization and DRAM bus utilization)	2020-12-22 12:33:45 -08:00
Blaise Tine	4bbd7bf408	performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,	2020-12-19 02:45:06 -08:00
Blaise Tine	d5438fd591	merging perf counters	2020-12-08 21:02:39 -08:00
Blaise Tine	2e0f51af80	fixed instr/cycle perf counter	2020-11-12 11:41:25 -08:00
Blaise Tine	112d8ab815	adding CSR support to rtlsim driver	2020-09-04 06:51:31 -04:00
Blaise Tine	e54425404e	fixed driver unrsolved dependencies	2020-08-27 06:41:40 -04:00
Blaise Tine	0b355f228e	ibuffer addition	2020-08-22 00:22:04 -07:00
Blaise Tine	2de61b5982	get device caps from CSRs	2020-06-30 00:08:23 -07:00
Blaise Tine	106d707024	verilator suppor for opae (partial)	2020-06-03 06:22:49 -04:00
Blaise Tine	9e5885b820	adding dram writeenable support + scheduler bug fixes	2020-05-27 19:00:23 -04:00
Blaise Tine	de9fc68ccc	opae fixes	2020-05-06 21:14:53 -07:00
Blaise Tine	a1dc90b951	rtl cache refactory	2020-04-30 17:12:18 -04:00
Blaise Tine	81745f08c9	added config.vh	2020-04-16 07:49:19 -04:00
Blaise Tine	12dc4d6874	refactoring fixes	2020-04-14 19:39:59 -04:00

Renamed from sw/driver/common/vx_utils.cpp (Browse further)