vortex/hw/rtl/cache
tinebp dfc7b6178c
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cleanup old cache test
2024-11-13 20:56:06 -08:00
..
VX_bank_flush.sv minor update 2024-10-19 22:14:38 -07:00
VX_cache.sv cleanup old cache test 2024-11-13 20:56:06 -08:00
VX_cache_bank.sv revert xilinx's asynchronous bram workaround 2024-10-24 01:44:55 -07:00
VX_cache_bypass.sv block ram redesign to support synthesizable write-first mode 2024-10-18 23:54:20 -07:00
VX_cache_cluster.sv disable sformatf during synthesis 2024-10-23 01:14:19 -07:00
VX_cache_data.sv revert xilinx's asynchronous bram workaround 2024-10-24 01:44:55 -07:00
VX_cache_define.vh cache hit timing optimization 2024-10-19 20:04:51 -07:00
VX_cache_flush.sv minor update 2024-10-19 22:14:38 -07:00
VX_cache_mshr.sv revert xilinx's asynchronous bram workaround 2024-10-24 01:44:55 -07:00
VX_cache_repl.sv revert xilinx's asynchronous bram workaround 2024-10-24 01:44:55 -07:00
VX_cache_tags.sv revert xilinx's asynchronous bram workaround 2024-10-24 01:44:55 -07:00
VX_cache_top.sv enabling Vivado's asynchronous bram suppot via direct netlist transformation 2024-11-13 16:20:25 -08:00
VX_cache_wrap.sv block ram redesign to support synthesizable write-first mode 2024-10-18 23:54:20 -07:00